State
Only PERIC0 has been (partially) wired to real CCF clocks on gs201 — enough for serial-getty@ttySAC0 to work over UART. Everything else stays as compatible = \"fixed-clock\" stubs with hardcoded rates.
Stubbed domains (from arch/arm64/boot/dts/exynos/google/gs201.dtsi after the bring-up commits):
- CMU_TOP, CMU_MIF
- CMU_HSI0 (USB power-island)
- CMU_HSI2 (UFS)
- CMU_DPU (display)
- CMU_AUD
- everything else
Patches that landed so far
0013 clk-samsung-gs101: add gs201 Tensor G2 CMU_TOP/CMU_MIF (scaffolding, not full)0014 clk-samsung-gs101: add gs201 CMU_PERIC0 + USI0_UART chains0015 tty/serial/samsung: add google,gs201-uart compat (UPIO_MEM32)
Working in tree but not yet upstream — see #3.
What we learned along the way
HSI2 CMU clk hypothesis is RULED OUT for the UFS HS-Rate-B wedge (#1). Direct ioremap probes (gated on GS201_PROBE_CMU_DIVIDERS) confirmed: HSI2 dividers/muxes/gates are byte-identical at post_link, pre_pwr_change, post_pwr_change in both PWM-G4 and HS-Rate-B G4 attempts. The bootloader programs them, neither AOSP nor mainline rewrites at PMC, and the fixed-clock stub rates accidentally match reality:
ufs_aclk stub claims 267 MHz; hardware NOC divider /2 of SHARED0_DIV4 = 266.5 MHz ✓ufs_unipro claims 177.664 MHz; UFS_EMBD divider /3 of SHARED0_DIV4 = 177.664 MHz ✓
So removing the stubs won't fix UFS HS. But the stubs are still wrong.
gs201 BL31 firewalls CMU access — kernel cmdline must include kvm-arm.mode=protected to unlock CMU readl. Without it, EL1 reads abort with synchronous external abort code 0x96000010. Documented at junkyard-boot-img/Makefile .build_boot.
Why finishing the CMU port matters
- devfreq scaling can't reason about anything without real CCF
- suspend / resume of the clock tree only works correctly with real parent/divider relationships
- New driver bring-up (DPU, GPU frequency, AOC) needs the relevant CMU domain wired before its driver can probe
- The gs201 PERIC0 quirks (DIV at 0x1808 not 0x1804, GATE at 0x20c0 not 0x20bc, no DBG mirror at base+0x4000 →
auto_clock_gate=true triggers SError) are the kind of thing that's easier to clean up while finishing other domains
Order of operations
Roughly: CMU_DPU is a prerequisite for #5 display bring-up; CMU_HSI0 is a prerequisite for any USB-host or USB-gadget work; CMU_HSI2 is a prerequisite for real UFS perf tuning even after HS-Rate-B (#1) is solved. CMU_AUD is on the AOC (#4) critical path.
State
Only PERIC0 has been (partially) wired to real CCF clocks on gs201 — enough for
serial-getty@ttySAC0to work over UART. Everything else stays ascompatible = \"fixed-clock\"stubs with hardcoded rates.Stubbed domains (from
arch/arm64/boot/dts/exynos/google/gs201.dtsiafter the bring-up commits):Patches that landed so far
0013clk-samsung-gs101: add gs201 Tensor G2 CMU_TOP/CMU_MIF (scaffolding, not full)0014clk-samsung-gs101: add gs201 CMU_PERIC0 + USI0_UART chains0015tty/serial/samsung: add google,gs201-uart compat (UPIO_MEM32)Working in tree but not yet upstream — see #3.
What we learned along the way
HSI2 CMU clk hypothesis is RULED OUT for the UFS HS-Rate-B wedge (#1). Direct ioremap probes (gated on
GS201_PROBE_CMU_DIVIDERS) confirmed: HSI2 dividers/muxes/gates are byte-identical at post_link, pre_pwr_change, post_pwr_change in both PWM-G4 and HS-Rate-B G4 attempts. The bootloader programs them, neither AOSP nor mainline rewrites at PMC, and the fixed-clock stub rates accidentally match reality:ufs_aclkstub claims 267 MHz; hardware NOC divider /2 of SHARED0_DIV4 = 266.5 MHz ✓ufs_uniproclaims 177.664 MHz; UFS_EMBD divider /3 of SHARED0_DIV4 = 177.664 MHz ✓So removing the stubs won't fix UFS HS. But the stubs are still wrong.
gs201 BL31 firewalls CMU access — kernel cmdline must include
kvm-arm.mode=protectedto unlock CMU readl. Without it, EL1 reads abort with synchronous external abort code 0x96000010. Documented at junkyard-boot-img/Makefile.build_boot.Why finishing the CMU port matters
auto_clock_gate=truetriggers SError) are the kind of thing that's easier to clean up while finishing other domainsOrder of operations
Roughly: CMU_DPU is a prerequisite for #5 display bring-up; CMU_HSI0 is a prerequisite for any USB-host or USB-gadget work; CMU_HSI2 is a prerequisite for real UFS perf tuning even after HS-Rate-B (#1) is solved. CMU_AUD is on the AOC (#4) critical path.