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gs201 felix UFS: HS-Rate-B wedges at every gear (PWM workaround active) #1

@ccrutchf

Description

@ccrutchf

State

UFS link is currently clamped to PWM-G4 via GS201_MAINLINE_FORCE_PWM_GEAR=4 in drivers/ufs/host/ufs-exynos.c. Throughput ~5–10 MB/s; enough for boot but a long-term performance debt.

What's broken

HS-Rate-B at every gear. PMC fully completes — host PA reports both lanes Connected/Active in FAST mode (verified by porting AOSP's exynos_ufs_get_caps_after_link + exynos_ufs_update_active_lanes as a read-only diagnostic; gated on GS201_PROBE_PA_STATE). Device acknowledges the mode change. First frame post-PMC then fails with dl_err 0x80000002 at +0.04s. The bug is below the PA layer — at M-PHY wire signaling, PCS calibration tuning, or a controller-internal handshake post-PMC that AOSP does and mainline doesn't.

PWM also has a controller bug. Any second of two back-to-back READ_10s wedges with zero error indication (saved_err=0x0, no pa_err/dl_err/nl_err/tl_err/dme_err), regardless of max_hw_sectors/queue_depth clamps. Wedge target LBA varies — high-LBA hypothesis was a coincidence. Workaround: rd.udev.children-max=1 cmdline serializes initrd workers enough to boot.

Diagnostic angles ruled out

  • PA layer / mode negotiation (S1)
  • HSI2 CMU divider/mux/gate state across PMC (C1/C2) — bootloader programs dividers correctly; fixed-clock stubs in dtsi accidentally match reality
  • EXYNOS_PD_HSI0 — verified to be a USB power-island driver, not UFS
  • AOSP-vs-mainline diff in cal-if walk — three missing writes ported (#9-#10 patches), END_UFS_PHY_CFG terminator added (#7), DESCTYPE=0 set (#11), GSA mailbox shim drafted (#8); none restored HS
  • AOSP felix and upstream scsi-for-next git bisect — no recent fix exists to port

Patches that landed in this tree

In branch felix on top of Linux 7.0:

  • 6c1643562877 drop UFSHCD_QUIRK_PRDT_BYTE_GRAN — UFS reaches HS-G4 L2
  • 3dcbb372fb8e two PMA register transcription typos + CDR-lock instrumentation
  • 22be7a6b669e AOSP-mechanism ports + diagnostic probes + PWM workaround
  • 87eb01375f30 add missing END_UFS_PHY_CFG terminator to pre_pwr_hs table
  • 1fffa2f504b8 KDN_CTRL_MON dump + GSA mailbox shim for KDN_SET_OP_MODE
  • bf87fea42f27 drop H8-entry writes from post_pwr_hs_config
  • 9c6216d5007d three missing writes from systematic cal-if walk
  • e3198717566b drop DESCTYPE probe loop, set FMPSECURITY0.DESCTYPE=0

Path forward

Outreach (Pixel team, Peter Griffin) is the only remaining lever — drafts queued in junkyard-boot-img/upstream-help/. AOSP boots gs201 UFS HS for some reason that isn't visible in the kernel source tree (BL31 handoff state, hardware-init timing, regulator/PD sequencing, or insider knowledge).

Why it matters

Restoring HS-Rate-B is a prerequisite for any perf-sensitive work on this device, and for full upstreaming of the gs201 felix patch series — GS201_MAINLINE_FORCE_PWM_GEAR is a non-shippable workaround.

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