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1. amba-ahb-master-slave-verilog-rtl amba-ahb-master-slave-verilog-rtl Public

   RTL design for the AMBA AHB protocol.

   SystemVerilog 8 3

2. amba-apb3-master-slave-verilog-rtl amba-apb3-master-slave-verilog-rtl Public

   The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )

   Verilog 17 5

3. crc-prallel-verilog-module-rtl-generator crc-prallel-verilog-module-rtl-generator Public

   Verilog parallel CRC generation module with custom polynomial and variable width

   Perl 6 2

4. rtl-boilerplate-code-generator rtl-boilerplate-code-generator Public

   Script to generate a verilog IP template for quick build ( supports makefile, compilefileist and more )

   Shell 3

5. std_module std_module Public

   All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.

   Verilog 3 1

6. prune_uvmg prune_uvmg Public

   GUI based UVM Test Environment generation tool

   Python 8 2