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[Arm64] ASIMD DotProduct and Rounding Double Multiply Add/Subtract #38957

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Merged
echesakov merged 23 commits into from
Jul 13, 2020
Merged

[Arm64] ASIMD DotProduct and Rounding Double Multiply Add/Subtract #38957

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6c9bc75
Add Dp.cs Dp.PlatformNotSupported.cs
echesakov Jun 30, 2020
b84568f
Add Rdm.cs Rdm.PlatformNotSupported.cs
echesakov Jul 7, 2020
6bb15f5
Add Dp.cs Dp.PlatformNotSupported.cs Rdm.cs Rdm.PlatformNotSupported.…
echesakov Jul 2, 2020
0fbb96a
Update System.Runtime.Intrinsics.cs
echesakov Jul 2, 2020
57dcd4f
Update PAL_GetJitCpuCapabilityFlags() in jitsupport.cpp
echesakov Jul 2, 2020
4d7b63c
Add InstructionSetDesc.txt
echesakov Jul 10, 2020
75ef984
Update jitinterface files
echesakov Jul 10, 2020
c48df72
Recognize Dp and Rdm classes as intrinsic containers in hwintrinsicar…
echesakov Jul 2, 2020
fb6851a
Add DotProduct and DotProductBySelectedQuadruplet in hwintrinsiclista…
echesakov Jul 2, 2020
7df470b
Add MultiplyRoundedDoublingAndAddSaturateHigh and MultiplyRoundedDoub…
echesakov Jul 7, 2020
c7cc928
Add DotProduct and DotProductBySelectedQuadruplet in GenerateTests.csx
echesakov Jul 8, 2020
f08bd97
Add MultiplyRoundedDoublingAndAddSaturateHigh and MultiplyRoundedDoub…
echesakov Jul 7, 2020
ba0f058
Whitespace formatting in GenerateTests.csx
echesakov Jul 8, 2020
8001bdc
Update Helpers.cs Helpers.tt
echesakov Jul 2, 2020
feb1bab
Update Shared/Program.cs
echesakov Jul 2, 2020
3313eb8
Add Dp/ Rdm/ Rdm.Arm64/
echesakov Jul 8, 2020
29da009
Update HardwareIntrinsics/Arm/
echesakov Jul 8, 2020
1e9ea9b
Update DotProductBySelectedQuadruplet in hwintrinsic.cpp hwintrinsicl…
echesakov Jul 9, 2020
2c46689
Exclude Rdm, Rdm.Arm64 and Dp tests from Mono in issues.targets
echesakov Jul 9, 2020
bc08993
Fix Dp.PlatformNotSupported.cs
echesakov Jul 9, 2020
6ba0b1b
Update HWIntrinsicInfo::isFullyImplementedIsa() in hwintrinsicarm64.cpp
echesakov Jul 10, 2020
3842467
Move Runtime_34587/ to src/tests/JIT/Regression/JitBlue/
echesakov Jul 10, 2020
a8bb36a
Update Runtime_34587 with Dp and Rdm
echesakov Jul 10, 2020
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52 changes: 41 additions & 11 deletions src/coreclr/src/inc/corinfoinstructionset.h
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Original file line number Diff line number Diff line change
Expand Up @@ -20,17 +20,21 @@ enum CORINFO_InstructionSet
InstructionSet_AdvSimd=2,
InstructionSet_Aes=3,
InstructionSet_Crc32=4,
InstructionSet_Sha1=5,
InstructionSet_Sha256=6,
InstructionSet_Atomics=7,
InstructionSet_Vector64=8,
InstructionSet_Vector128=9,
InstructionSet_ArmBase_Arm64=10,
InstructionSet_AdvSimd_Arm64=11,
InstructionSet_Aes_Arm64=12,
InstructionSet_Crc32_Arm64=13,
InstructionSet_Sha1_Arm64=14,
InstructionSet_Sha256_Arm64=15,
InstructionSet_Dp=5,
InstructionSet_Rdm=6,
InstructionSet_Sha1=7,
InstructionSet_Sha256=8,
InstructionSet_Atomics=9,
InstructionSet_Vector64=10,
InstructionSet_Vector128=11,
InstructionSet_ArmBase_Arm64=12,
InstructionSet_AdvSimd_Arm64=13,
InstructionSet_Aes_Arm64=14,
InstructionSet_Crc32_Arm64=15,
InstructionSet_Dp_Arm64=16,
InstructionSet_Rdm_Arm64=17,
InstructionSet_Sha1_Arm64=18,
InstructionSet_Sha256_Arm64=19,
#endif // TARGET_ARM64
#ifdef TARGET_AMD64
InstructionSet_X86Base=1,
Expand Down Expand Up @@ -158,6 +162,10 @@ struct CORINFO_InstructionSetFlags
AddInstructionSet(InstructionSet_Aes_Arm64);
if (HasInstructionSet(InstructionSet_Crc32))
AddInstructionSet(InstructionSet_Crc32_Arm64);
if (HasInstructionSet(InstructionSet_Dp))
AddInstructionSet(InstructionSet_Dp_Arm64);
if (HasInstructionSet(InstructionSet_Rdm))
AddInstructionSet(InstructionSet_Rdm_Arm64);
if (HasInstructionSet(InstructionSet_Sha1))
AddInstructionSet(InstructionSet_Sha1_Arm64);
if (HasInstructionSet(InstructionSet_Sha256))
Expand Down Expand Up @@ -237,6 +245,14 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_Crc32);
if (resultflags.HasInstructionSet(InstructionSet_Crc32_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Crc32))
resultflags.RemoveInstructionSet(InstructionSet_Crc32_Arm64);
if (resultflags.HasInstructionSet(InstructionSet_Dp) && !resultflags.HasInstructionSet(InstructionSet_Dp_Arm64))
resultflags.RemoveInstructionSet(InstructionSet_Dp);
if (resultflags.HasInstructionSet(InstructionSet_Dp_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Dp))
resultflags.RemoveInstructionSet(InstructionSet_Dp_Arm64);
if (resultflags.HasInstructionSet(InstructionSet_Rdm) && !resultflags.HasInstructionSet(InstructionSet_Rdm_Arm64))
resultflags.RemoveInstructionSet(InstructionSet_Rdm);
if (resultflags.HasInstructionSet(InstructionSet_Rdm_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Rdm))
resultflags.RemoveInstructionSet(InstructionSet_Rdm_Arm64);
if (resultflags.HasInstructionSet(InstructionSet_Sha1) && !resultflags.HasInstructionSet(InstructionSet_Sha1_Arm64))
resultflags.RemoveInstructionSet(InstructionSet_Sha1);
if (resultflags.HasInstructionSet(InstructionSet_Sha1_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Sha1))
Expand All @@ -251,6 +267,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_Aes);
if (resultflags.HasInstructionSet(InstructionSet_Crc32) && !resultflags.HasInstructionSet(InstructionSet_ArmBase))
resultflags.RemoveInstructionSet(InstructionSet_Crc32);
if (resultflags.HasInstructionSet(InstructionSet_Dp) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd))
resultflags.RemoveInstructionSet(InstructionSet_Dp);
if (resultflags.HasInstructionSet(InstructionSet_Rdm) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd))
resultflags.RemoveInstructionSet(InstructionSet_Rdm);
if (resultflags.HasInstructionSet(InstructionSet_Sha1) && !resultflags.HasInstructionSet(InstructionSet_ArmBase))
resultflags.RemoveInstructionSet(InstructionSet_Sha1);
if (resultflags.HasInstructionSet(InstructionSet_Sha256) && !resultflags.HasInstructionSet(InstructionSet_ArmBase))
Expand Down Expand Up @@ -415,6 +435,14 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
return "Crc32";
case InstructionSet_Crc32_Arm64 :
return "Crc32_Arm64";
case InstructionSet_Dp :
return "Dp";
case InstructionSet_Dp_Arm64 :
return "Dp_Arm64";
case InstructionSet_Rdm :
return "Rdm";
case InstructionSet_Rdm_Arm64 :
return "Rdm_Arm64";
case InstructionSet_Sha1 :
return "Sha1";
case InstructionSet_Sha1_Arm64 :
Expand Down Expand Up @@ -561,6 +589,8 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
case READYTORUN_INSTRUCTION_AdvSimd: return InstructionSet_AdvSimd;
case READYTORUN_INSTRUCTION_Aes: return InstructionSet_Aes;
case READYTORUN_INSTRUCTION_Crc32: return InstructionSet_Crc32;
case READYTORUN_INSTRUCTION_Dp: return InstructionSet_Dp;
case READYTORUN_INSTRUCTION_Rdm: return InstructionSet_Rdm;
case READYTORUN_INSTRUCTION_Sha1: return InstructionSet_Sha1;
case READYTORUN_INSTRUCTION_Sha256: return InstructionSet_Sha256;
case READYTORUN_INSTRUCTION_Atomics: return InstructionSet_Atomics;
Expand Down
2 changes: 2 additions & 0 deletions src/coreclr/src/inc/readytoruninstructionset.h
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,8 @@ enum ReadyToRunInstructionSet
READYTORUN_INSTRUCTION_Sha256=20,
READYTORUN_INSTRUCTION_Atomics=21,
READYTORUN_INSTRUCTION_X86Base=22,
READYTORUN_INSTRUCTION_Dp=23,
READYTORUN_INSTRUCTION_Rdm=24,

};

Expand Down
8 changes: 8 additions & 0 deletions src/coreclr/src/jit/hwintrinsic.cpp
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Expand Up @@ -914,6 +914,14 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
{
assert(numArgs == 4);
indexedElementBaseType = getBaseTypeAndSizeOfSIMDType(sigReader.op3ClsHnd, &indexedElementSimdSize);

if (intrinsic == NI_Dp_DotProductBySelectedQuadruplet)
{
assert(((baseType == TYP_INT) && (indexedElementBaseType == TYP_BYTE)) ||
((baseType == TYP_UINT) && (indexedElementBaseType == TYP_UBYTE)));
// The second source operand of sdot, udot instructions is an indexed 32-bit element.
indexedElementBaseType = baseType;
}
}

assert(indexedElementBaseType == baseType);
Expand Down
26 changes: 22 additions & 4 deletions src/coreclr/src/jit/hwintrinsicarm64.cpp
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Expand Up @@ -26,10 +26,14 @@ static CORINFO_InstructionSet Arm64VersionOfIsa(CORINFO_InstructionSet isa)
return InstructionSet_ArmBase_Arm64;
case InstructionSet_Crc32:
return InstructionSet_Crc32_Arm64;
case InstructionSet_Dp:
return InstructionSet_Dp_Arm64;
case InstructionSet_Sha1:
return InstructionSet_Sha1_Arm64;
case InstructionSet_Sha256:
return InstructionSet_Sha256_Arm64;
case InstructionSet_Rdm:
return InstructionSet_Rdm_Arm64;
default:
return InstructionSet_NONE;
}
Expand Down Expand Up @@ -69,6 +73,20 @@ static CORINFO_InstructionSet lookupInstructionSet(const char* className)
return InstructionSet_Crc32;
}
}
else if (className[0] == 'D')
{
if (strcmp(className, "Dp") == 0)
{
return InstructionSet_Dp;
}
}
else if (className[0] == 'R')
{
if (strcmp(className, "Rdm") == 0)
{
return InstructionSet_Rdm;
}
}
else if (className[0] == 'S')
{
if (strcmp(className, "Sha1") == 0)
Expand Down Expand Up @@ -140,20 +158,20 @@ bool HWIntrinsicInfo::isFullyImplementedIsa(CORINFO_InstructionSet isa)
case InstructionSet_ArmBase_Arm64:
case InstructionSet_Crc32:
case InstructionSet_Crc32_Arm64:
case InstructionSet_Dp:
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@tannergooding tannergooding Jul 10, 2020

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Missing Dp_Arm64?

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@echesakov echesakov Jul 10, 2020

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Fixed

case InstructionSet_Dp_Arm64:
case InstructionSet_Rdm:
case InstructionSet_Rdm_Arm64:
case InstructionSet_Sha1:
case InstructionSet_Sha1_Arm64:
case InstructionSet_Sha256:
case InstructionSet_Sha256_Arm64:
case InstructionSet_Vector64:
case InstructionSet_Vector128:
{
return true;
}

default:
{
return false;
}
}
}

Expand Down
28 changes: 28 additions & 0 deletions src/coreclr/src/jit/hwintrinsiclistarm64.h
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Expand Up @@ -544,6 +544,34 @@ HARDWARE_INTRINSIC(Crc32, ComputeCrc32C,
HARDWARE_INTRINSIC(Crc32_Arm64, ComputeCrc32, 0, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_crc32x, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_NoFloatingPointUsed|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(Crc32_Arm64, ComputeCrc32C, 0, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_crc32cx, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_NoFloatingPointUsed|HW_Flag_SpecialCodeGen)

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size Number of arguments Instructions Category Flags
// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// DP Intrinsics
HARDWARE_INTRINSIC(Dp, DotProduct, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sdot, INS_udot, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Dp, DotProductBySelectedQuadruplet, -1, 4, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sdot, INS_udot, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDByIndexedElement, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size Number of arguments Instructions Category Flags
// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// RDM Intrinsics
HARDWARE_INTRINSIC(Rdm, MultiplyRoundedDoublingAndAddSaturateHigh, -1, 3, {INS_invalid, INS_invalid, INS_sqrdmlah, INS_invalid, INS_sqrdmlah, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Rdm, MultiplyRoundedDoublingAndSubtractSaturateHigh, -1, 3, {INS_invalid, INS_invalid, INS_sqrdmlsh, INS_invalid, INS_sqrdmlsh, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Rdm, MultiplyRoundedDoublingBySelectedScalarAndAddSaturateHigh, -1, 4, {INS_invalid, INS_invalid, INS_sqrdmlah, INS_invalid, INS_sqrdmlah, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDByIndexedElement, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Rdm, MultiplyRoundedDoublingBySelectedScalarAndSubtractSaturateHigh, -1, 4, {INS_invalid, INS_invalid, INS_sqrdmlsh, INS_invalid, INS_sqrdmlsh, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDByIndexedElement, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size Number of arguments Instructions Category Flags
// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// RDM 64-bit only Intrinsics
HARDWARE_INTRINSIC(Rdm_Arm64, MultiplyRoundedDoublingAndAddSaturateHighScalar, 8, 3, {INS_invalid, INS_invalid, INS_sqrdmlah, INS_invalid, INS_sqrdmlah, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(Rdm_Arm64, MultiplyRoundedDoublingAndSubtractSaturateHighScalar, 8, 3, {INS_invalid, INS_invalid, INS_sqrdmlsh, INS_invalid, INS_sqrdmlsh, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(Rdm_Arm64, MultiplyRoundedDoublingScalarBySelectedScalarAndAddSaturateHigh, 8, 4, {INS_invalid, INS_invalid, INS_sqrdmlah, INS_invalid, INS_sqrdmlah, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDByIndexedElement, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(Rdm_Arm64, MultiplyRoundedDoublingScalarBySelectedScalarAndSubtractSaturateHigh, 8, 4, {INS_invalid, INS_invalid, INS_sqrdmlsh, INS_invalid, INS_sqrdmlsh, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDByIndexedElement, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar)

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size Number of arguments Instructions Category Flags
// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
Expand Down
8 changes: 4 additions & 4 deletions src/coreclr/src/pal/src/misc/jitsupport.cpp
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Expand Up @@ -50,8 +50,8 @@ PAL_GetJitCpuCapabilityFlags(CORJIT_FLAGS *flags)
// CPUCompileFlags.Set(CORJIT_FLAGS::CORJIT_FLAG_HAS_ARM64_DCPOP);
#endif
#ifdef HWCAP_ASIMDDP
// if (hwCap & HWCAP_ASIMDDP)
// CPUCompileFlags.Set(CORJIT_FLAGS::CORJIT_FLAG_HAS_ARM64_DP);
if (hwCap & HWCAP_ASIMDDP)
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@tannergooding tannergooding Jul 9, 2020

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We should add a tracking issue with the tracking-external-issue label for when Windows support is in, so we can update the codeman checks for Windows.

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@echesakov echesakov Jul 10, 2020

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Done #39094

CPUCompileFlags.Set(InstructionSet_Dp);
#endif
#ifdef HWCAP_FCMA
// if (hwCap & HWCAP_FCMA)
Expand Down Expand Up @@ -98,8 +98,8 @@ PAL_GetJitCpuCapabilityFlags(CORJIT_FLAGS *flags)
CPUCompileFlags.Set(InstructionSet_AdvSimd);
#endif
#ifdef HWCAP_ASIMDRDM
// if (hwCap & HWCAP_ASIMDRDM)
// CPUCompileFlags.Set(CORJIT_FLAGS::CORJIT_FLAG_HAS_ARM64_ADVSIMD_V81);
if (hwCap & HWCAP_ASIMDRDM)
CPUCompileFlags.Set(InstructionSet_Rdm);
#endif
#ifdef HWCAP_ASIMDHP
// if (hwCap & HWCAP_ASIMDHP)
Expand Down
2 changes: 2 additions & 0 deletions src/coreclr/src/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs
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Expand Up @@ -34,6 +34,8 @@ public enum ReadyToRunInstructionSet
Sha256=20,
Atomics=21,
X86Base=22,
Dp=23,
Rdm=24,

}
}
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