Arm64: cmn & neg shifted register instructions are not generated for LSR

[jonathandavies-arm]

These 2 instructions were said to be completed in #68028 but I writing tests for them and found the following issue. See #111796 for the full tests.

These 2 c# functions should produce similar output disassembly.

static int NegLSL(int a)
{
    return -(a<<2);
}

static uint NegLSR(uint a)
{
    return (uint)-(a>>20);
}

NegLSL produces a single instruction neg w0, w0, LSL #2
NegLSR produces the following:

lsr     w0, w0, #20
mov     w0, w0
neg     w0, w0

This happens because a CAST node is in between the NEG & RSZ nodes and when we run the lowering phase it can't set the RSZ node as contained.

STMT00000 ( 0x000[E-] ... ??? )
               [000006] -----------                         *  RETURN    int   
               [000005] -----------                         \--*  CAST      int <- uint <- long
               [000004] -----------                            \--*  NEG       long  
               [000003] ---------U-                               \--*  CAST      long <- ulong <- uint
               [000002] -----------                                  \--*  RSZ       int   
               [000000] -----------                                     +--*  LCL_VAR   int    V00 arg0         
               [000001] -----------                                     \--*  CNS_INT   int    20

Compare this to the node tree of the NegLSL function. After lowering the LSH node is contained and the shifted neg is output.

STMT00000 ( 0x000[E-] ... ??? )
               [000004] -----------                         *  RETURN    int   
               [000003] -----------                         \--*  NEG       int   
               [000002] -----------                            \--*  LSH       int   
               [000000] -----------                               +--*  LCL_VAR   int    V00 arg0         
               [000001] -----------                               \--*  CNS_INT   int    2

This happens for cmn with a LSR as well.

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[kunalspathak]

Just to be clear, the issue is because of CAST node and the problem repros regardless of bit operation involved.

e.g.

    static uint NegLSL_un(uint a)
    {
        return (uint)-(a << 2);
    }