AArch64 base algorithm refactoring in LLVM#6907
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mbaret merged 6 commits intoapache:mainfrom Nov 23, 2020
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Perhaps slightly more explanation on the add-pair part of the intrinsic, otherwise looks like a significant improvement.
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cc @FrozenGene @yzhliu if you're interested |
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Nov 19, 2020
This PR stemmed from apache#6907 and it is fixing a small error in the getter and setter of a buffer for the case where `t.lanes > 1`. I also added a test to stress the issue.
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Nov 19, 2020
This PR stemmed from apache#6907 and it is fixing a small error in the getter and setter of a buffer for the case where `t.lanes > 1`. I also added a test to stress the issue.
giuseros
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Nov 19, 2020
This PR stemmed from apache#6907 and it is fixing a small error in the getter and setter of a buffer for the case where `t.lanes > 1`. I also added a test to stress the issue.
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This PR stemmed from apache#6907 and it is fixing a small error in the getter and setter of a buffer for the case where `t.lanes > 1`. I also added a test to stress the issue.
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* Bug-fix] Fix tir allocation with multiple lanes This PR stemmed from #6907 and it is fixing a small error in the getter and setter of a buffer for the case where `t.lanes > 1`. I also added a test to stress the issue. * Address dtyped vs non-dtyped constant cases
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November 20, 2020 10:55
- I refactored the assembly in arm_cpu/tensor_intrin.py to use LLVM+TIR - Removed the `interleave` boolean parameter in the intrinsic to switch among two different interleaving modes. LLVM will now take care of interleaving the instructions - Applied the changes accordingly to conv2d_gemm.py to call the right instrinsic Note: I found LLVM very sensible to the choice of the `-mcpu`. So, in order to preserve performance, it is important to specify the right `-mcpu` when creating the LLVM target
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Just some final comments on the docstrings.
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This is now merged, thanks @giuseros ! |
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Dec 2, 2020
* Bug-fix] Fix tir allocation with multiple lanes This PR stemmed from apache#6907 and it is fixing a small error in the getter and setter of a buffer for the case where `t.lanes > 1`. I also added a test to stress the issue. * Address dtyped vs non-dtyped constant cases
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Dec 2, 2020
* AArch64 base algorithm refactoring in LLVM - I refactored the assembly in arm_cpu/tensor_intrin.py to use LLVM+TIR - Removed the `interleave` boolean parameter in the intrinsic to switch among two different interleaving modes. LLVM will now take care of interleaving the instructions - Applied the changes accordingly to conv2d_gemm.py to call the right instrinsic Note: I found LLVM very sensible to the choice of the `-mcpu`. So, in order to preserve performance, it is important to specify the right `-mcpu` when creating the LLVM target * Fix linting * Fix linting -2 * Fixing comments * Address review comments * Fix spaces around ':' in docstrings
trevor-m
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Dec 4, 2020
* Bug-fix] Fix tir allocation with multiple lanes This PR stemmed from apache#6907 and it is fixing a small error in the getter and setter of a buffer for the case where `t.lanes > 1`. I also added a test to stress the issue. * Address dtyped vs non-dtyped constant cases
trevor-m
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Dec 4, 2020
* AArch64 base algorithm refactoring in LLVM - I refactored the assembly in arm_cpu/tensor_intrin.py to use LLVM+TIR - Removed the `interleave` boolean parameter in the intrinsic to switch among two different interleaving modes. LLVM will now take care of interleaving the instructions - Applied the changes accordingly to conv2d_gemm.py to call the right instrinsic Note: I found LLVM very sensible to the choice of the `-mcpu`. So, in order to preserve performance, it is important to specify the right `-mcpu` when creating the LLVM target * Fix linting * Fix linting -2 * Fixing comments * Address review comments * Fix spaces around ':' in docstrings
trevor-m
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Dec 4, 2020
* Bug-fix] Fix tir allocation with multiple lanes This PR stemmed from apache#6907 and it is fixing a small error in the getter and setter of a buffer for the case where `t.lanes > 1`. I also added a test to stress the issue. * Address dtyped vs non-dtyped constant cases
trevor-m
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Dec 4, 2020
* AArch64 base algorithm refactoring in LLVM - I refactored the assembly in arm_cpu/tensor_intrin.py to use LLVM+TIR - Removed the `interleave` boolean parameter in the intrinsic to switch among two different interleaving modes. LLVM will now take care of interleaving the instructions - Applied the changes accordingly to conv2d_gemm.py to call the right instrinsic Note: I found LLVM very sensible to the choice of the `-mcpu`. So, in order to preserve performance, it is important to specify the right `-mcpu` when creating the LLVM target * Fix linting * Fix linting -2 * Fixing comments * Address review comments * Fix spaces around ':' in docstrings
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interleaveboolean parameter in the intrinsic to switchamong two different interleaving modes. LLVM will now take care of
interleaving the instructions
instrinsic
Note: I found LLVM very sensible to the choice of the
-mcpu.So, in order to preserve performance, it is important to specify the
right
-mcpuwhen creating the LLVM target