[Hexagon] Adapt some intrinsics for high vector lanes#14345
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masahi merged 4 commits intoapache:mainfrom Mar 27, 2023
Merged
[Hexagon] Adapt some intrinsics for high vector lanes#14345masahi merged 4 commits intoapache:mainfrom
masahi merged 4 commits intoapache:mainfrom
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@ibsidorenko FYI |
apeskov
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Signed-off-by: Alexander Peskov <peskovnn@gmail.com>
Signed-off-by: Alexander Peskov <peskovnn@gmail.com>
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@masahi @kparzysz-quic @jverma-quic Previously you reviewed patches like this. Could you please take a look on this one? |
ibsidorenko
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Mar 21, 2023
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Please polish doc writing in general.
| Will accept vector lanes equal orig_vec_lanes * 2**n for n in [0,1,2...] | ||
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| Ada is equivalent of splitting input args to chunk with lanes equal orig_vec_lanes, | ||
| execution provided low_intrinsic for each of them and concatenate back. |
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Also please polish this sentence, it is broken.
| Intrinsic implementation to adapt | ||
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| intrinsic_lanes: int | ||
| Args lanes supported by provided intrinsic |
masahi
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Mar 24, 2023
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@tvm-bot rerun |
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Goal is to allow to apply intrinsics "q_multiply_shift" and "q_multiply_shift_per_axis" for vector type i32x128. Originally it supports only "i32x32" which is natively supported by platform (1024 bit vector).
Motivation
There are situation than we have to use vector size slightly more than supported by platform. As example consider sequence of element-wise operators: add -> q_multiply_shift -> cast. To achieve performance we have to squash it into one single loop (
sch.compute_at(...)). First two operators would like to be vectorised with using data type "int32x32". last one cast operator want to use i32x128 as src and i8x128 as dst. As result we have to adapt all this operator to accept vector size "??x128" to successfully vectorise entire loop.This change allows to achieve significant performance speedup for tuning tasks like
conv -> add -> qnn.requantize -> cast_i8.