[TIR] Vectorized buffer elements and indices#12
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Lunderberg wants to merge 2 commits intoapache:mainfrom
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[TIR] Vectorized buffer elements and indices#12Lunderberg wants to merge 2 commits intoapache:mainfrom
Lunderberg wants to merge 2 commits intoapache:mainfrom
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Closing, pending pre-RFC at https://discuss.tvm.apache.org/t/pre-rfc-vectorized-tir-buffers/10615 |
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I put this together following TVM PR#8528, which resolved an issue with array access in the Vulkan runtime, but led to/exposed some inconsistencies in the TIR semantics for buffer indices. Vulkan/SPIR-V require all arrays to be typed, and doesn't allow type casts that would be permissible in C code, such as casting between
float32*andfloat32x2*. As a result, any vectorized load/store operations must act on an array whose elements are vectorized types.Currently, many places in IR (e.g.
Load::Loadchecking the number of output lanes) and codegen (e.g.CodeGenC'sLoadNodeloop over output lanes rather than element/index lanes) implicitly assume that all array elements havelanes == 1.I couldn't find any documentation on intended semantics for these multi-lane array indices, and so I wanted to propose, discuss, and document the intended semantics.