The schematic doesn't provide any information to the user about which of the capacitors on the lines are populated.
I can confirm that C296 and C297 are placed, because I can drive the transceiver with 125MHz clock on FPGA_REF_CLK1_P/N
Sidenote: It is slightly confusing that FPGA_REF_CLK1 goes to MGT_REF_0 .. Not a big deal I suppose.
The schematic doesn't provide any information to the user about which of the capacitors on the lines are populated.
I can confirm that C296 and C297 are placed, because I can drive the transceiver with 125MHz clock on FPGA_REF_CLK1_P/N
Sidenote: It is slightly confusing that FPGA_REF_CLK1 goes to MGT_REF_0 .. Not a big deal I suppose.