Search results

PULP DIVSQRT output handshake stability bug

Status: Open.

#180 In openhwgroup/cvfpu;

· baselkelziye opened on Aug 2, 2026

DivSqrtSel=PULP gives wrong result vs DivSqrtSel=THMULTI for RUP/RDN/RMM

Status: Open.

#178 In openhwgroup/cvfpu;

· hailinzeng opened on Jul 27, 2026

[Bug] Minor issue in the C910 DivSqrt rtl

Status: Open.

#174 In openhwgroup/cvfpu;

· ashraf629 opened on Jul 21, 2026

[BUG] BFloat16: Special Underflow case in DIV

Status: Open.

#169 In openhwgroup/cvfpu;

· Whitenix opened on May 19, 2026

Document 'vendorization' process for this repo

Documentation

Status: Open.

#159 In openhwgroup/cvfpu;

· MikeOpenHWGroup opened on Mar 5, 2026

PULP divsqrt unit does not produce correct results and stalls the unit with busy signal high

Status: Open.

#152 In openhwgroup/cvfpu;

· wedeha opened on Aug 14, 2025

Undefined width of reg_ena_i at fpnew_divsqrt_multi

Status: Open.

#144 In openhwgroup/cvfpu;

· redpanda3 opened on Nov 14, 2024

Out of bound signals generated by yosys

Status: Open.

#143 In openhwgroup/cvfpu;

· redpanda3 opened on Nov 6, 2024

[BUG] NX flag not correctly triggered in specific cases

Status: Open.

#139 In openhwgroup/cvfpu;

· fly-1011 opened on Aug 22, 2024

[BUG] Incorrectly set fflags: An underflow exception is triggered when the computed result is an exact subnormal number.

Status: Open.

#121 In openhwgroup/cvfpu;

· fly-1011 opened on May 18, 2024

[BUG] Incorrect fflags Set When Using fdiv Instruction to Divide by Infinity

Status: Open.

#120 In openhwgroup/cvfpu;

· fly-1011 opened on May 15, 2024

SQRT operation for FP16ALT only works when all op[n] lanes are assigned to the same input

Status: Open.

#117 In openhwgroup/cvfpu;

· selimsandal opened on May 12, 2024