diff --git a/src/coreclr/jit/codegenarm64test.cpp b/src/coreclr/jit/codegenarm64test.cpp index 3a7bd859a9e9e5..e1d5087ad193e3 100644 --- a/src/coreclr/jit/codegenarm64test.cpp +++ b/src/coreclr/jit/codegenarm64test.cpp @@ -4753,6 +4753,28 @@ void CodeGen::genArm64EmitterUnitTestsSve() theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_R3, REG_P6, REG_V9, INS_OPTS_SCALABLE_D_WITH_SCALAR); /* CLASTB , , , . */ + // IF_SVE_CX_4A + theEmitter->emitIns_R_R_R_R(INS_sve_cmpeq, EA_SCALABLE, REG_P15, REG_P0, REG_V0, REG_V10, + INS_OPTS_SCALABLE_B); /* CMPEQ ., /Z, ., . */ + theEmitter->emitIns_R_R_R_R(INS_sve_cmpge, EA_SCALABLE, REG_P14, REG_P1, REG_V10, REG_V23, + INS_OPTS_SCALABLE_H); /* CMPGE ., /Z, ., . */ + theEmitter->emitIns_R_R_R_R(INS_sve_cmpgt, EA_SCALABLE, REG_P13, REG_P2, REG_V20, REG_V24, + INS_OPTS_SCALABLE_S); /* CMPGT ., /Z, ., . */ + theEmitter->emitIns_R_R_R_R(INS_sve_cmphi, EA_SCALABLE, REG_P12, REG_P3, REG_V30, REG_V25, + INS_OPTS_SCALABLE_D); /* CMPHI ., /Z, ., . */ + theEmitter->emitIns_R_R_R_R(INS_sve_cmphs, EA_SCALABLE, REG_P11, REG_P4, REG_V1, REG_V26, + INS_OPTS_SCALABLE_B); /* CMPHS ., /Z, ., . */ + theEmitter->emitIns_R_R_R_R(INS_sve_cmple, EA_SCALABLE, REG_P10, REG_P5, REG_V11, REG_V27, + INS_OPTS_SCALABLE_H); /* CMPLE ., /Z, ., . */ + theEmitter->emitIns_R_R_R_R(INS_sve_cmplo, EA_SCALABLE, REG_P11, REG_P6, REG_V12, REG_V28, + INS_OPTS_SCALABLE_S); /* CMPLO ., /Z, ., . */ + theEmitter->emitIns_R_R_R_R(INS_sve_cmpls, EA_SCALABLE, REG_P0, REG_P7, REG_V13, REG_V29, + INS_OPTS_SCALABLE_D); /* CMPLS ., /Z, ., . */ + theEmitter->emitIns_R_R_R_R(INS_sve_cmplt, EA_SCALABLE, REG_P2, REG_P0, REG_V14, REG_V30, + INS_OPTS_SCALABLE_B); /* CMPLT ., /Z, ., . */ + theEmitter->emitIns_R_R_R_R(INS_sve_cmpne, EA_SCALABLE, REG_P3, REG_P1, REG_V15, REG_V20, + INS_OPTS_SCALABLE_H); /* CMPNE ., /Z, ., . */ + // IF_SVE_EP_3A theEmitter->emitIns_R_R_R(INS_sve_shadd, EA_SCALABLE, REG_V15, REG_P0, REG_V10, INS_OPTS_SCALABLE_B); /* SHADD ., /M, ., . */ diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 709ab8659be71f..1f41cddb8642c2 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -1041,6 +1041,16 @@ void emitter::emitInsSanityCheck(instrDesc* id) assert(isValidScalarDatasize(elemsize)); break; + case IF_SVE_CX_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors + elemsize = id->idOpSize(); + assert(insOptsScalableSimple(id->idInsOpt())); // xx + assert(isPredicateRegister(id->idReg1())); // DDDD + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm + assert(isVectorRegister(id->idReg4())); // nnnnn + assert(isScalableVectorSize(elemsize)); + break; + // Scalable FP. case IF_SVE_GR_3A: // ........xx...... ...gggmmmmmddddd -- SVE2 floating-point pairwise operations case IF_SVE_HL_3A: // ........xx...... ...gggmmmmmddddd -- SVE floating-point arithmetic (predicated) @@ -1176,6 +1186,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) assert(isVectorRegister(id->idReg1())); // nnnn assert(isVectorRegister(id->idReg2())); // ddddd assert(id->idInsOpt() == INS_OPTS_SCALABLE_H); + assert(isScalableVectorSize(elemsize)); break; case IF_SVE_GD_2A: // .........x.xx... ......nnnnnddddd -- SVE2 saturating extract narrow @@ -9818,8 +9829,13 @@ void emitter::emitIns_R_R_I_I( * Add an instruction referencing four registers. */ -void emitter::emitIns_R_R_R_R( - instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, regNumber reg4) +void emitter::emitIns_R_R_R_R(instruction ins, + emitAttr attr, + regNumber reg1, + regNumber reg2, + regNumber reg3, + regNumber reg4, + insOpts opt /* = INS_OPT_NONE*/) { emitAttr size = EA_SIZE(attr); insFormat fmt = IF_NONE; @@ -9858,16 +9874,59 @@ void emitter::emitIns_R_R_R_R( fmt = IF_NONE; break; + case INS_sve_cmpeq: + case INS_sve_cmpgt: + case INS_sve_cmpge: + case INS_sve_cmphi: + case INS_sve_cmphs: + case INS_sve_cmpne: + case INS_sve_cmple: + case INS_sve_cmplo: + case INS_sve_cmpls: + case INS_sve_cmplt: + assert(insOptsScalableSimple(opt)); + assert(isPredicateRegister(reg1)); // DDDD + assert(isLowPredicateRegister(reg2)); // ggg + assert(isVectorRegister(reg3)); // mmmmm + assert(isVectorRegister(reg4)); // nnnnn + assert(isScalableVectorSize(attr)); // xx + fmt = IF_SVE_CX_4A; + break; + default: unreached(); break; } assert(fmt != IF_NONE); + // Use aliases. + switch (ins) + { + case INS_sve_cmple: + std::swap(reg3, reg4); + ins = INS_sve_cmpge; + break; + case INS_sve_cmplo: + std::swap(reg3, reg4); + ins = INS_sve_cmphi; + break; + case INS_sve_cmpls: + std::swap(reg3, reg4); + ins = INS_sve_cmphs; + break; + case INS_sve_cmplt: + std::swap(reg3, reg4); + ins = INS_sve_cmpgt; + break; + default: + break; + } + instrDesc* id = emitNewInstr(attr); id->idIns(ins); id->idInsFmt(fmt); + id->idInsOpt(opt); id->idReg1(reg1); id->idReg2(reg2); @@ -11768,15 +11827,15 @@ void emitter::emitIns_Call(EmitCallType callType, /***************************************************************************** * - * Return an encoding for the specified 'V' register used in '20' thru '17' position. + * Return an encoding for the specified 'V' register used in '20' thru '16' position. */ -/*static*/ emitter::code_t emitter::insEncodeReg_V_20_to_17(regNumber reg) +/*static*/ emitter::code_t emitter::insEncodeReg_V_20_to_16(regNumber reg) { assert(isVectorRegister(reg)); emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0; assert((ureg >= 0) && (ureg <= 32)); - return ureg << 17; + return ureg << 16; } /***************************************************************************** @@ -14720,6 +14779,16 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp) dst += emitOutput_Instr(dst, code); break; + case IF_SVE_CX_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors + code = emitInsCodeSve(ins, fmt); + code |= insEncodeReg_P_3_to_0(id->idReg1()); // DDDD + code |= insEncodeReg_P_12_to_10(id->idReg2()); // ggg + code |= insEncodeReg_V_9_to_5(id->idReg3()); // mmmmm + code |= insEncodeReg_V_20_to_16(id->idReg4()); // nnnnn + code |= insEncodeElemsize(optGetSveElemsize(id->idInsOpt())); // xx + dst += emitOutput_Instr(dst, code); + break; + case IF_SVE_GA_2A: // ............iiii ......nnnn.ddddd -- SME2 multi-vec shift narrow imm = emitGetInsSC(id); assert(id->idInsOpt() == INS_OPTS_SCALABLE_H); @@ -15333,7 +15402,7 @@ void emitter::emitDispSveRegList(regNumber firstReg, unsigned listSize, insOpts //------------------------------------------------------------------------ // emitDispPredicateReg: Display a predicate register name with with an arrangement suffix // -void emitter::emitDispPredicateReg(regNumber reg, PredicateType ptype, bool addComma) +void emitter::emitDispPredicateReg(regNumber reg, PredicateType ptype, insOpts opt, bool addComma) { assert(isPredicateRegister(reg)); printf(emitPredicateRegName(reg)); @@ -15346,6 +15415,10 @@ void emitter::emitDispPredicateReg(regNumber reg, PredicateType ptype, bool addC { printf("/z"); } + else if (ptype == PREDICATE_SIZED) + { + emitDispElemsize(optGetSveElemsize(opt)); + } if (addComma) emitDispComma(); @@ -15354,11 +15427,11 @@ void emitter::emitDispPredicateReg(regNumber reg, PredicateType ptype, bool addC //------------------------------------------------------------------------ // emitDispLowPredicateReg: Display a low predicate register name with with an arrangement suffix // -void emitter::emitDispLowPredicateReg(regNumber reg, PredicateType ptype, bool addComma) +void emitter::emitDispLowPredicateReg(regNumber reg, PredicateType ptype, insOpts opt, bool addComma) { assert(isLowPredicateRegister(reg)); reg = (regNumber)((((unsigned)reg - REG_PREDICATE_FIRST) & 0x7) + REG_PREDICATE_FIRST); - emitDispPredicateReg(reg, ptype, addComma); + emitDispPredicateReg(reg, ptype, opt, addComma); } //------------------------------------------------------------------------ @@ -17001,10 +17074,10 @@ void emitter::emitDispInsHelp( // (predicated) case IF_SVE_GR_3A: // ........xx...... ...gggmmmmmddddd -- SVE2 floating-point pairwise operations case IF_SVE_HL_3A: // ........xx...... ...gggmmmmmddddd -- SVE floating-point arithmetic (predicated) - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispLowPredicateReg(id->idReg2(), PREDICATE_MERGE, true); // ggg - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispLowPredicateReg(id->idReg2(), PREDICATE_MERGE, id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; // ., /, . @@ -17012,34 +17085,34 @@ void emitter::emitDispInsHelp( { PredicateType ptype = (insOptsScalableWithPredicateMerge(id->idInsOpt())) ? PREDICATE_MERGE : PREDICATE_ZERO; - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // nnnnn - emitDispLowPredicateReg(id->idReg2(), ptype, true); // ggg - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // ddddd + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // nnnnn + emitDispLowPredicateReg(id->idReg2(), ptype, id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // ddddd break; } // ., /M, ., # case IF_SVE_AM_2A: // ........xx...... ...gggxxiiiddddd -- SVE bitwise shift by immediate (predicated) - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispLowPredicateReg(id->idReg2(), PREDICATE_MERGE, true); // ggg - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispImm(emitGetInsSC(id), false); // iiii + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispLowPredicateReg(id->idReg2(), PREDICATE_MERGE, id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispImm(emitGetInsSC(id), false); // iiii break; // ., /M, ., .D case IF_SVE_AO_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by wide elements (predicated) - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispLowPredicateReg(id->idReg2(), PREDICATE_MERGE, true); // ggg - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispSveReg(id->idReg3(), INS_OPTS_SCALABLE_D, false); // mmmmm + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispLowPredicateReg(id->idReg2(), PREDICATE_MERGE, id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispSveReg(id->idReg3(), INS_OPTS_SCALABLE_D, false); // mmmmm break; // ., , ., . case IF_SVE_CM_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally broadcast element to vector - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispLowPredicateReg(id->idReg2(), PREDICATE_NONE, true); // ggg - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispLowPredicateReg(id->idReg2(), PREDICATE_NONE, id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; // , , , . @@ -17047,10 +17120,10 @@ void emitter::emitDispInsHelp( case IF_SVE_CN_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to SIMD&FP scalar case IF_SVE_CO_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to general register case IF_SVE_HJ_3A: // ........xx...... ...gggmmmmmddddd -- SVE floating-point serial reduction (predicated) - emitDispReg(id->idReg1(), size, true); // ddddd - emitDispLowPredicateReg(id->idReg2(), PREDICATE_NONE, true); // ggg - emitDispReg(id->idReg1(), size, true); // ddddd - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispReg(id->idReg1(), size, true); // ddddd + emitDispLowPredicateReg(id->idReg2(), PREDICATE_NONE, id->idInsOpt(), true); // ggg + emitDispReg(id->idReg1(), size, true); // ddddd + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; // , , . @@ -17060,9 +17133,9 @@ void emitter::emitDispInsHelp( case IF_SVE_CR_3A: // ........xx...... ...gggnnnnnddddd -- SVE extract element to SIMD&FP scalar register case IF_SVE_CS_3A: // ........xx...... ...gggnnnnnddddd -- SVE extract element to general register case IF_SVE_HE_3A: // ........xx...... ...gggnnnnnddddd -- SVE floating-point recursive reduction - emitDispReg(id->idReg1(), size, true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, true); // ggg - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispReg(id->idReg1(), size, true); // ddddd + emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; // ., , . @@ -17070,16 +17143,16 @@ void emitter::emitDispInsHelp( case IF_SVE_AJ_3A: // ........xx...... ...gggnnnnnddddd -- SVE integer add reduction (quadwords) case IF_SVE_AL_3A: // ........xx...... ...gggnnnnnddddd -- SVE integer min/max reduction (quadwords) case IF_SVE_GS_3A: // ........xx...... ...gggnnnnnddddd -- SVE floating-point recursive reduction (quadwords) - emitDispVectorReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, true); // ggg - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispVectorReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; //
, , . case IF_SVE_AI_3A: // ........xx...... ...gggnnnnnddddd -- SVE integer add reduction (predicated) - emitDispReg(id->idReg1(), EA_8BYTE, true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, true); // ggg - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispReg(id->idReg1(), EA_8BYTE, true); // ddddd + emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; // ., /M, . @@ -17089,37 +17162,45 @@ void emitter::emitDispInsHelp( case IF_SVE_ES_3A: // ........xx...... ...gggnnnnnddddd -- SVE2 integer unary operations (predicated) case IF_SVE_HQ_3A: // ........xx...... ...gggnnnnnddddd -- SVE floating-point round to integral value case IF_SVE_HR_3A: // ........xx...... ...gggnnnnnddddd -- SVE floating-point unary operations - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_MERGE, true); // ggg - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispPredicateReg(id->idReg2(), PREDICATE_MERGE, id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; // ., , . case IF_SVE_CL_3A: // ........xx...... ...gggnnnnnddddd -- SVE compress active elements - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, true); // ggg - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; // ., /M, case IF_SVE_CP_3A: // ........xx...... ...gggnnnnnddddd -- SVE copy SIMD&FP scalar register to vector // (predicated) - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_MERGE, true); // ggg - emitDispReg(id->idReg3(), size, false); // mmmmm + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispPredicateReg(id->idReg2(), PREDICATE_MERGE, id->idInsOpt(), true); // ggg + emitDispReg(id->idReg3(), size, false); // mmmmm break; // ., /M, case IF_SVE_CQ_3A: // ........xx...... ...gggnnnnnddddd -- SVE copy general register to vector (predicated) - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_MERGE, true); // ggg - emitDispReg(encodingZRtoSP(id->idReg3()), size, false); // mmmmm + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispPredicateReg(id->idReg2(), PREDICATE_MERGE, id->idInsOpt(), true); // ggg + emitDispReg(encodingZRtoSP(id->idReg3()), size, false); // mmmmm + break; + + // ., /Z, ., . + case IF_SVE_CX_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors + emitDispPredicateReg(id->idReg1(), PREDICATE_SIZED, id->idInsOpt(), true); // DDDD + emitDispPredicateReg(id->idReg2(), PREDICATE_ZERO, id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), id->idInsOpt(), true); // mmmmm + emitDispSveReg(id->idReg4(), id->idInsOpt(), false); // nnnnn break; // ., /M, . case IF_SVE_EQ_3A: // ........xx...... ...gggnnnnnddddd -- SVE2 integer pairwise add and accumulate long emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispLowPredicateReg(id->idReg2(), PREDICATE_MERGE, true); // ggg + emitDispLowPredicateReg(id->idReg2(), PREDICATE_MERGE, id->idInsOpt(), true); // ggg emitDispSveReg(id->idReg3(), (insOpts)((unsigned)id->idInsOpt() - 1), false); // mmmmm break; @@ -19474,6 +19555,11 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins result.insThroughput = PERFSCORE_THROUGHPUT_1C; break; + case IF_SVE_CX_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors + result.insLatency = PERFSCORE_LATENCY_4C; + result.insThroughput = PERFSCORE_THROUGHPUT_1C; + break; + // Extract/insert operation, SIMD and FP scalar form case IF_SVE_CR_3A: // ........xx...... ...gggnnnnnddddd -- SVE extract element to SIMD&FP scalar register result.insLatency = PERFSCORE_LATENCY_3C; diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index 44f6814334a19a..84964b284ba004 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -24,6 +24,7 @@ enum PredicateType PREDICATE_NONE = 0, PREDICATE_MERGE, PREDICATE_ZERO, + PREDICATE_SIZED, }; const char* emitSveRegName(regNumber reg); @@ -53,8 +54,8 @@ void emitDispVectorRegIndex(regNumber reg, emitAttr elemsize, ssize_t index, boo void emitDispVectorRegList(regNumber firstReg, unsigned listSize, insOpts opt, bool addComma); void emitDispVectorElemList(regNumber firstReg, unsigned listSize, emitAttr elemsize, unsigned index, bool addComma); void emitDispSveRegList(regNumber firstReg, unsigned listSize, insOpts opt, bool addComma); -void emitDispPredicateReg(regNumber reg, PredicateType ptype, bool addComma); -void emitDispLowPredicateReg(regNumber reg, PredicateType ptype, bool addComma); +void emitDispPredicateReg(regNumber reg, PredicateType ptype, insOpts opt, bool addComma); +void emitDispLowPredicateReg(regNumber reg, PredicateType ptype, insOpts opt, bool addComma); void emitDispArrangement(insOpts opt); void emitDispElemsize(emitAttr elemsize); void emitDispShiftedReg(regNumber reg, insOpts opt, ssize_t imm, emitAttr attr); @@ -376,8 +377,8 @@ static code_t insEncodePredQualifier_16(bool merge); // Return an encoding for the specified 'V' register used in '19' thru '17' position. static code_t insEncodeReg_V_19_to_17(regNumber reg); -// Return an encoding for the specified 'V' register used in '20' thru '17' position. -static code_t insEncodeReg_V_20_to_17(regNumber reg); +// Return an encoding for the specified 'V' register used in '20' thru '16' position. +static code_t insEncodeReg_V_20_to_16(regNumber reg); // Return an encoding for the specified 'V' register used in '9' thru '6' position. static code_t insEncodeReg_V_9_to_6(regNumber reg); @@ -1053,7 +1054,13 @@ void emitIns_R_R_R_Ext(instruction ins, void emitIns_R_R_I_I( instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, int imm1, int imm2, insOpts opt = INS_OPTS_NONE); -void emitIns_R_R_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, regNumber reg4); +void emitIns_R_R_R_R(instruction ins, + emitAttr attr, + regNumber reg1, + regNumber reg2, + regNumber reg3, + regNumber reg4, + insOpts opt = INS_OPTS_NONE); void emitIns_R_COND(instruction ins, emitAttr attr, regNumber reg, insCond cond);