diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp
index 8c474c3b9d8166..fd52f0b02eabb2 100644
--- a/src/coreclr/jit/emitarm64.cpp
+++ b/src/coreclr/jit/emitarm64.cpp
@@ -1417,7 +1417,7 @@ const char* emitter::emitRegName(regNumber reg, emitAttr size, bool varName) con
         }
         else if (size == EA_SCALABLE)
         {
-            rn = zRegNames[reg - REG_V0];
+            rn = zRegNames[reg - REG_Z0];
         }
     }
 
@@ -1437,9 +1437,9 @@ const char* emitter::emitRegName(regNumber reg, emitAttr size, bool varName) con
 //
 const char* emitter::emitSveRegName(regNumber reg)
 {
-    assert((reg >= REG_V0) && (reg <= REG_V31));
+    assert((reg >= REG_Z0) && (reg <= REG_Z31));
 
-    int index = (int)reg - (int)REG_V0;
+    int index = (int)reg - (int)REG_Z0;
 
     return zRegNames[index];
 }
diff --git a/src/coreclr/jit/registerarm64.h b/src/coreclr/jit/registerarm64.h
index e8c126fac148cb..84f821236147f9 100644
--- a/src/coreclr/jit/registerarm64.h
+++ b/src/coreclr/jit/registerarm64.h
@@ -94,6 +94,39 @@ REGDEF(V29,  29+VBASE, VMASK(29), "d29", "s29")
 REGDEF(V30,  30+VBASE, VMASK(30), "d30", "s30")
 REGDEF(V31,  31+VBASE, VMASK(31), "d31", "s31")
 
+REGALIAS(Z0, V0)
+REGALIAS(Z1, V1)
+REGALIAS(Z2, V2)
+REGALIAS(Z3, V3)
+REGALIAS(Z4, V4)
+REGALIAS(Z5, V5)
+REGALIAS(Z6, V6)
+REGALIAS(Z7, V7)
+REGALIAS(Z8, V8)
+REGALIAS(Z9, V9)
+REGALIAS(Z10, V10)
+REGALIAS(Z11, V11)
+REGALIAS(Z12, V12)
+REGALIAS(Z13, V13)
+REGALIAS(Z14, V14)
+REGALIAS(Z15, V15)
+REGALIAS(Z16, V16)
+REGALIAS(Z17, V17)
+REGALIAS(Z18, V18)
+REGALIAS(Z19, V19)
+REGALIAS(Z20, V20)
+REGALIAS(Z21, V21)
+REGALIAS(Z22, V22)
+REGALIAS(Z23, V23)
+REGALIAS(Z24, V24)
+REGALIAS(Z25, V25)
+REGALIAS(Z26, V26)
+REGALIAS(Z27, V27)
+REGALIAS(Z28, V28)
+REGALIAS(Z29, V29)
+REGALIAS(Z30, V30)
+REGALIAS(Z31, V31)
+
 // TODO-SVE: Fix once we add predicate registers
 REGALIAS(P0, V0)
 REGALIAS(P1, V1)