From 4ad982f6ea032573336eefe8a8a35d0c58aaf2e7 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Tue, 7 Nov 2023 14:58:22 +0000 Subject: [PATCH 1/4] Add empty SVE API for Arm64 --- src/coreclr/inc/clrconfigvalues.h | 1 + src/coreclr/inc/corinfoinstructionset.h | 31 ++++++++--- src/coreclr/inc/jiteeversionguid.h | 12 ++--- src/coreclr/inc/readytoruninstructionset.h | 1 + src/coreclr/jit/CMakeLists.txt | 1 + src/coreclr/jit/compiler.cpp | 5 ++ src/coreclr/jit/hwintrinsicarm64.cpp | 8 +++ src/coreclr/jit/hwintrinsiclistarm64.h | 2 + src/coreclr/jit/hwintrinsiclistarm64sve.h | 23 ++++++++ src/coreclr/jit/jitconfigvalues.h | 1 + .../Compiler/HardwareIntrinsicHelpers.cs | 5 ++ .../Runtime/ReadyToRunInstructionSet.cs | 1 + .../Runtime/ReadyToRunInstructionSetHelper.cs | 2 + .../JitInterface/CorInfoInstructionSet.cs | 40 +++++++++++--- .../ThunkGenerator/InstructionSetDesc.txt | 3 ++ src/coreclr/vm/codeman.cpp | 5 ++ .../ILLink.Substitutions.NoArmIntrinsics.xml | 6 +++ .../System.Private.CoreLib.Shared.projitems | 2 + .../Arm/Sve.PlatformNotSupported.cs | 30 +++++++++++ .../src/System/Runtime/Intrinsics/Arm/Sve.cs | 32 +++++++++++ .../ref/System.Runtime.Intrinsics.cs | 11 ++++ src/native/minipal/cpufeatures.c | 3 ++ src/native/minipal/cpufeatures.h | 1 + .../JIT/HardwareIntrinsics/Arm/Sve/Program.cs | 53 +++++++++++++++++++ .../JIT/HardwareIntrinsics/Arm/Sve/Sve.csproj | 15 ++++++ 25 files changed, 272 insertions(+), 22 deletions(-) create mode 100644 src/coreclr/jit/hwintrinsiclistarm64sve.h create mode 100644 src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs create mode 100644 src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs create mode 100644 src/tests/JIT/HardwareIntrinsics/Arm/Sve/Program.cs create mode 100644 src/tests/JIT/HardwareIntrinsics/Arm/Sve/Sve.csproj diff --git a/src/coreclr/inc/clrconfigvalues.h b/src/coreclr/inc/clrconfigvalues.h index c556d45c495894..8be4aaa8eeef4f 100644 --- a/src/coreclr/inc/clrconfigvalues.h +++ b/src/coreclr/inc/clrconfigvalues.h @@ -798,6 +798,7 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sha1, W("EnableArm64Sh RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sha256, W("EnableArm64Sha256"), 1, "Allows Arm64 Sha256+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Rcpc, W("EnableArm64Rcpc"), 1, "Allows Arm64 Rcpc+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Rcpc2, W("EnableArm64Rcpc2"), 1, "Allows Arm64 Rcpc2+ hardware intrinsics to be disabled") +RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sve, W("EnableArm64Sve"), 1, "Allows Arm64 SVE hardware intrinsics to be disabled") #endif /// diff --git a/src/coreclr/inc/corinfoinstructionset.h b/src/coreclr/inc/corinfoinstructionset.h index 2ffd9bf6873201..e24bfab038ce0a 100644 --- a/src/coreclr/inc/corinfoinstructionset.h +++ b/src/coreclr/inc/corinfoinstructionset.h @@ -31,14 +31,16 @@ enum CORINFO_InstructionSet InstructionSet_Rcpc=13, InstructionSet_VectorT128=14, InstructionSet_Rcpc2=15, - InstructionSet_ArmBase_Arm64=16, - InstructionSet_AdvSimd_Arm64=17, - InstructionSet_Aes_Arm64=18, - InstructionSet_Crc32_Arm64=19, - InstructionSet_Dp_Arm64=20, - InstructionSet_Rdm_Arm64=21, - InstructionSet_Sha1_Arm64=22, - InstructionSet_Sha256_Arm64=23, + InstructionSet_Sve=16, + InstructionSet_ArmBase_Arm64=17, + InstructionSet_AdvSimd_Arm64=18, + InstructionSet_Aes_Arm64=19, + InstructionSet_Crc32_Arm64=20, + InstructionSet_Dp_Arm64=21, + InstructionSet_Rdm_Arm64=22, + InstructionSet_Sha1_Arm64=23, + InstructionSet_Sha256_Arm64=24, + InstructionSet_Sve_Arm64=25, #endif // TARGET_ARM64 #ifdef TARGET_AMD64 InstructionSet_X86Base=1, @@ -282,6 +284,8 @@ struct CORINFO_InstructionSetFlags AddInstructionSet(InstructionSet_Sha1_Arm64); if (HasInstructionSet(InstructionSet_Sha256)) AddInstructionSet(InstructionSet_Sha256_Arm64); + if (HasInstructionSet(InstructionSet_Sve)) + AddInstructionSet(InstructionSet_Sve_Arm64); #endif // TARGET_ARM64 #ifdef TARGET_AMD64 if (HasInstructionSet(InstructionSet_X86Base)) @@ -394,6 +398,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins resultflags.RemoveInstructionSet(InstructionSet_Sha256); if (resultflags.HasInstructionSet(InstructionSet_Sha256_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Sha256)) resultflags.RemoveInstructionSet(InstructionSet_Sha256_Arm64); + if (resultflags.HasInstructionSet(InstructionSet_Sve) && !resultflags.HasInstructionSet(InstructionSet_Sve_Arm64)) + resultflags.RemoveInstructionSet(InstructionSet_Sve); + if (resultflags.HasInstructionSet(InstructionSet_Sve_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Sve)) + resultflags.RemoveInstructionSet(InstructionSet_Sve_Arm64); if (resultflags.HasInstructionSet(InstructionSet_AdvSimd) && !resultflags.HasInstructionSet(InstructionSet_ArmBase)) resultflags.RemoveInstructionSet(InstructionSet_AdvSimd); if (resultflags.HasInstructionSet(InstructionSet_Aes) && !resultflags.HasInstructionSet(InstructionSet_ArmBase)) @@ -414,6 +422,8 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins resultflags.RemoveInstructionSet(InstructionSet_Vector128); if (resultflags.HasInstructionSet(InstructionSet_VectorT128) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd)) resultflags.RemoveInstructionSet(InstructionSet_VectorT128); + if (resultflags.HasInstructionSet(InstructionSet_Sve) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd)) + resultflags.RemoveInstructionSet(InstructionSet_Sve); #endif // TARGET_ARM64 #ifdef TARGET_AMD64 if (resultflags.HasInstructionSet(InstructionSet_X86Base) && !resultflags.HasInstructionSet(InstructionSet_X86Base_X64)) @@ -764,6 +774,10 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet) return "VectorT128"; case InstructionSet_Rcpc2 : return "Rcpc2"; + case InstructionSet_Sve : + return "Sve"; + case InstructionSet_Sve_Arm64 : + return "Sve_Arm64"; #endif // TARGET_ARM64 #ifdef TARGET_AMD64 case InstructionSet_X86Base : @@ -998,6 +1012,7 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst case READYTORUN_INSTRUCTION_Rcpc: return InstructionSet_Rcpc; case READYTORUN_INSTRUCTION_VectorT128: return InstructionSet_VectorT128; case READYTORUN_INSTRUCTION_Rcpc2: return InstructionSet_Rcpc2; + case READYTORUN_INSTRUCTION_Sve: return InstructionSet_Sve; #endif // TARGET_ARM64 #ifdef TARGET_AMD64 case READYTORUN_INSTRUCTION_X86Base: return InstructionSet_X86Base; diff --git a/src/coreclr/inc/jiteeversionguid.h b/src/coreclr/inc/jiteeversionguid.h index 70960ff577ee8a..139ec31efae5d4 100644 --- a/src/coreclr/inc/jiteeversionguid.h +++ b/src/coreclr/inc/jiteeversionguid.h @@ -43,13 +43,13 @@ typedef const GUID *LPCGUID; #define GUID_DEFINED #endif // !GUID_DEFINED -constexpr GUID JITEEVersionIdentifier = { /* a2974440-e8ee-4d95-9e6e-799a330be1a0 */ - 0xa2974440, - 0xe8ee, - 0x4d95, - {0x9e, 0x6e, 0x79, 0x9a, 0x33, 0x0b, 0xe1, 0xa0} +constexpr GUID JITEEVersionIdentifier = { /* e15e62ce-d9c6-418a-a5a7-26ad17fcf4bf */ + 0xe15e62ce, + 0xd9c6, + 0x418a, + {0xa5, 0xa7, 0x26, 0xad, 0x17, 0xfc, 0xf4, 0xbf} }; - + ////////////////////////////////////////////////////////////////////////////////////////////////////////// // // END JITEEVersionIdentifier diff --git a/src/coreclr/inc/readytoruninstructionset.h b/src/coreclr/inc/readytoruninstructionset.h index 190fe4b516617e..4ec3b030ae5bbb 100644 --- a/src/coreclr/inc/readytoruninstructionset.h +++ b/src/coreclr/inc/readytoruninstructionset.h @@ -51,6 +51,7 @@ enum ReadyToRunInstructionSet READYTORUN_INSTRUCTION_VectorT256=40, READYTORUN_INSTRUCTION_VectorT512=41, READYTORUN_INSTRUCTION_Rcpc2=42, + READYTORUN_INSTRUCTION_Sve=43, }; diff --git a/src/coreclr/jit/CMakeLists.txt b/src/coreclr/jit/CMakeLists.txt index 1931228fca66c5..a1b8cbb9a249de 100644 --- a/src/coreclr/jit/CMakeLists.txt +++ b/src/coreclr/jit/CMakeLists.txt @@ -400,6 +400,7 @@ set( JIT_ARM64_HEADERS emitfmtsarm64.h emitfmtsarm64sve.h hwintrinsiclistarm64.h + hwintrinsiclistarm64sve.h instrsarm64.h instrsarm64sve.h registerarm64.h diff --git a/src/coreclr/jit/compiler.cpp b/src/coreclr/jit/compiler.cpp index 355403baa92684..d4509bab4e6560 100644 --- a/src/coreclr/jit/compiler.cpp +++ b/src/coreclr/jit/compiler.cpp @@ -6013,6 +6013,11 @@ int Compiler::compCompile(CORINFO_MODULE_HANDLE classPtr, { instructionSetFlags.AddInstructionSet(InstructionSet_Dczva); } + + if (JitConfig.EnableArm64Sve() != 0) + { + instructionSetFlags.AddInstructionSet(InstructionSet_Sve); + } #elif defined(TARGET_XARCH) if (JitConfig.EnableHWIntrinsic() != 0) { diff --git a/src/coreclr/jit/hwintrinsicarm64.cpp b/src/coreclr/jit/hwintrinsicarm64.cpp index 3ac9792c8eb072..3394e24373bb3f 100644 --- a/src/coreclr/jit/hwintrinsicarm64.cpp +++ b/src/coreclr/jit/hwintrinsicarm64.cpp @@ -34,6 +34,8 @@ static CORINFO_InstructionSet Arm64VersionOfIsa(CORINFO_InstructionSet isa) return InstructionSet_Sha256_Arm64; case InstructionSet_Rdm: return InstructionSet_Rdm_Arm64; + case InstructionSet_Sve: + return InstructionSet_Sve_Arm64; default: return InstructionSet_NONE; } @@ -97,6 +99,10 @@ static CORINFO_InstructionSet lookupInstructionSet(const char* className) { return InstructionSet_Sha256; } + if (strcmp(className, "Sve") == 0) + { + return InstructionSet_Sve; + } } else if (className[0] == 'V') { @@ -166,6 +172,8 @@ bool HWIntrinsicInfo::isFullyImplementedIsa(CORINFO_InstructionSet isa) case InstructionSet_Sha1_Arm64: case InstructionSet_Sha256: case InstructionSet_Sha256_Arm64: + case InstructionSet_Sve: + case InstructionSet_Sve_Arm64: case InstructionSet_Vector64: case InstructionSet_Vector128: return true; diff --git a/src/coreclr/jit/hwintrinsiclistarm64.h b/src/coreclr/jit/hwintrinsiclistarm64.h index 699184d7a99738..889e77591c4ad2 100644 --- a/src/coreclr/jit/hwintrinsiclistarm64.h +++ b/src/coreclr/jit/hwintrinsiclistarm64.h @@ -795,6 +795,8 @@ HARDWARE_INTRINSIC(Sha256, ScheduleUpdate1, #endif // FEATURE_HW_INTRINSIC +#include "hwintrinsiclistarm64sve.h" + #undef HARDWARE_INTRINSIC // clang-format on diff --git a/src/coreclr/jit/hwintrinsiclistarm64sve.h b/src/coreclr/jit/hwintrinsiclistarm64sve.h new file mode 100644 index 00000000000000..52767bf90249f4 --- /dev/null +++ b/src/coreclr/jit/hwintrinsiclistarm64sve.h @@ -0,0 +1,23 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +/*****************************************************************************/ +#ifndef HARDWARE_INTRINSIC +#error Define HARDWARE_INTRINSIC before including this file +#endif +/*****************************************************************************/ + +// clang-format off + +#ifdef FEATURE_HW_INTRINSICS +// *************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************** +// ISA Function name SIMD size NumArg EncodesExtraTypeArg Instructions Category Flags +// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE} +// *************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************** +// SVE Intrinsics + +#endif // FEATURE_HW_INTRINSIC + +#undef HARDWARE_INTRINSIC + +// clang-format on diff --git a/src/coreclr/jit/jitconfigvalues.h b/src/coreclr/jit/jitconfigvalues.h index 65afd348819e11..38279e6853c1af 100644 --- a/src/coreclr/jit/jitconfigvalues.h +++ b/src/coreclr/jit/jitconfigvalues.h @@ -351,6 +351,7 @@ CONFIG_INTEGER(EnableArm64Dp, W("EnableArm64Dp"), 1) / CONFIG_INTEGER(EnableArm64Rdm, W("EnableArm64Rdm"), 1) // Allows Arm64 Rdm+ hardware intrinsics to be disabled CONFIG_INTEGER(EnableArm64Sha1, W("EnableArm64Sha1"), 1) // Allows Arm64 Sha1+ hardware intrinsics to be disabled CONFIG_INTEGER(EnableArm64Sha256, W("EnableArm64Sha256"), 1) // Allows Arm64 Sha256+ hardware intrinsics to be disabled +CONFIG_INTEGER(EnableArm64Sve, W("EnableArm64Sve"), 1) // Allows Arm64 Sve+ hardware intrinsics to be disabled #endif // clang-format on diff --git a/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs b/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs index 1e778e97c67f3e..c30736fcb6019d 100644 --- a/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs +++ b/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs @@ -221,6 +221,7 @@ private static class Arm64IntrinsicConstants public const int Rcpc = 0x0100; public const int VectorT128 = 0x0200; public const int Rcpc2 = 0x0400; + public const int Sve = 0x0800; public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags) { @@ -244,6 +245,8 @@ public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags) builder.AddSupportedInstructionSet("rcpc"); if ((flags & Rcpc2) != 0) builder.AddSupportedInstructionSet("rcpc2"); + if ((flags & Sve) != 0) + builder.AddSupportedInstructionSet("sve"); } public static int FromInstructionSet(InstructionSet instructionSet) @@ -273,6 +276,8 @@ public static int FromInstructionSet(InstructionSet instructionSet) InstructionSet.ARM64_Atomics => Atomics, InstructionSet.ARM64_Rcpc => Rcpc, InstructionSet.ARM64_Rcpc2 => Rcpc2, + InstructionSet.ARM64_Sve => Sve, + InstructionSet.ARM64_Sve_Arm64 => Sve, // Vector Sizes InstructionSet.ARM64_VectorT128 => VectorT128, diff --git a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs index 51c1a4854d71f4..284131d1641acc 100644 --- a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs +++ b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs @@ -54,6 +54,7 @@ public enum ReadyToRunInstructionSet VectorT256=40, VectorT512=41, Rcpc2=42, + Sve=43, } } diff --git a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs index 57629f66b9c6f5..7000b482ec604a 100644 --- a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs +++ b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs @@ -46,6 +46,8 @@ public static class ReadyToRunInstructionSetHelper case InstructionSet.ARM64_Rcpc: return ReadyToRunInstructionSet.Rcpc; case InstructionSet.ARM64_VectorT128: return ReadyToRunInstructionSet.VectorT128; case InstructionSet.ARM64_Rcpc2: return ReadyToRunInstructionSet.Rcpc2; + case InstructionSet.ARM64_Sve: return ReadyToRunInstructionSet.Sve; + case InstructionSet.ARM64_Sve_Arm64: return ReadyToRunInstructionSet.Sve; default: throw new Exception("Unknown instruction set"); } diff --git a/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs b/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs index d7bc2e56ebd2a4..a5398c85ca0758 100644 --- a/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs +++ b/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs @@ -31,6 +31,7 @@ public enum InstructionSet ARM64_Rcpc = InstructionSet_ARM64.Rcpc, ARM64_VectorT128 = InstructionSet_ARM64.VectorT128, ARM64_Rcpc2 = InstructionSet_ARM64.Rcpc2, + ARM64_Sve = InstructionSet_ARM64.Sve, ARM64_ArmBase_Arm64 = InstructionSet_ARM64.ArmBase_Arm64, ARM64_AdvSimd_Arm64 = InstructionSet_ARM64.AdvSimd_Arm64, ARM64_Aes_Arm64 = InstructionSet_ARM64.Aes_Arm64, @@ -39,6 +40,7 @@ public enum InstructionSet ARM64_Rdm_Arm64 = InstructionSet_ARM64.Rdm_Arm64, ARM64_Sha1_Arm64 = InstructionSet_ARM64.Sha1_Arm64, ARM64_Sha256_Arm64 = InstructionSet_ARM64.Sha256_Arm64, + ARM64_Sve_Arm64 = InstructionSet_ARM64.Sve_Arm64, X64_X86Base = InstructionSet_X64.X86Base, X64_SSE = InstructionSet_X64.SSE, X64_SSE2 = InstructionSet_X64.SSE2, @@ -187,14 +189,16 @@ public enum InstructionSet_ARM64 Rcpc = 13, VectorT128 = 14, Rcpc2 = 15, - ArmBase_Arm64 = 16, - AdvSimd_Arm64 = 17, - Aes_Arm64 = 18, - Crc32_Arm64 = 19, - Dp_Arm64 = 20, - Rdm_Arm64 = 21, - Sha1_Arm64 = 22, - Sha256_Arm64 = 23, + Sve = 16, + ArmBase_Arm64 = 17, + AdvSimd_Arm64 = 18, + Aes_Arm64 = 19, + Crc32_Arm64 = 20, + Dp_Arm64 = 21, + Rdm_Arm64 = 22, + Sha1_Arm64 = 23, + Sha256_Arm64 = 24, + Sve_Arm64 = 25, } public enum InstructionSet_X64 @@ -525,6 +529,10 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target resultflags.AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64); if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sha256_Arm64)) resultflags.AddInstructionSet(InstructionSet.ARM64_Sha256); + if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve)) + resultflags.AddInstructionSet(InstructionSet.ARM64_Sve_Arm64); + if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve_Arm64)) + resultflags.AddInstructionSet(InstructionSet.ARM64_Sve); if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd)) resultflags.AddInstructionSet(InstructionSet.ARM64_ArmBase); if (resultflags.HasInstructionSet(InstructionSet.ARM64_Aes)) @@ -545,6 +553,8 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd); if (resultflags.HasInstructionSet(InstructionSet.ARM64_VectorT128)) resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd); + if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve)) + resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd); break; case TargetArchitecture.X64: @@ -874,6 +884,8 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe resultflags.AddInstructionSet(InstructionSet.ARM64_Sha1); if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sha256_Arm64)) resultflags.AddInstructionSet(InstructionSet.ARM64_Sha256); + if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve_Arm64)) + resultflags.AddInstructionSet(InstructionSet.ARM64_Sve); if (resultflags.HasInstructionSet(InstructionSet.ARM64_ArmBase)) resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd); if (resultflags.HasInstructionSet(InstructionSet.ARM64_ArmBase)) @@ -894,6 +906,8 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe resultflags.AddInstructionSet(InstructionSet.ARM64_Vector128); if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd)) resultflags.AddInstructionSet(InstructionSet.ARM64_VectorT128); + if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd)) + resultflags.AddInstructionSet(InstructionSet.ARM64_Sve); break; case TargetArchitecture.X64: @@ -1198,6 +1212,7 @@ public static IEnumerable ArchitectureToValidInstructionSets yield return new InstructionSetInfo("rcpc", "", InstructionSet.ARM64_Rcpc, true); yield return new InstructionSetInfo("vectort128", "VectorT128", InstructionSet.ARM64_VectorT128, true); yield return new InstructionSetInfo("rcpc2", "", InstructionSet.ARM64_Rcpc2, true); + yield return new InstructionSetInfo("sve", "Sve", InstructionSet.ARM64_Sve, true); break; case TargetArchitecture.X64: @@ -1300,6 +1315,8 @@ public void Set64BitInstructionSetVariants(TargetArchitecture architecture) AddInstructionSet(InstructionSet.ARM64_Sha1_Arm64); if (HasInstructionSet(InstructionSet.ARM64_Sha256)) AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64); + if (HasInstructionSet(InstructionSet.ARM64_Sve)) + AddInstructionSet(InstructionSet.ARM64_Sve_Arm64); break; case TargetArchitecture.X64: @@ -1382,6 +1399,7 @@ public void Set64BitInstructionSetVariantsUnconditionally(TargetArchitecture arc AddInstructionSet(InstructionSet.ARM64_Rdm_Arm64); AddInstructionSet(InstructionSet.ARM64_Sha1_Arm64); AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64); + AddInstructionSet(InstructionSet.ARM64_Sve_Arm64); break; case TargetArchitecture.X64: @@ -1551,6 +1569,12 @@ public static InstructionSet LookupPlatformIntrinsicInstructionSet(TargetArchite case "VectorT128": { return InstructionSet.ARM64_VectorT128; } + case "Sve": + if (nestedTypeName == "Arm64") + { return InstructionSet.ARM64_Sve_Arm64; } + else + { return InstructionSet.ARM64_Sve; } + } break; diff --git a/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt b/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt index ba4db589c81a0f..7b6e15b87bd84a 100644 --- a/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt +++ b/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt @@ -168,6 +168,7 @@ instructionset ,ARM64 , , , ,Dczva instructionset ,ARM64 , ,Rcpc ,26 ,Rcpc ,rcpc instructionset ,ARM64 ,VectorT128 , ,39 ,VectorT128 ,vectort128 instructionset ,ARM64 , ,Rcpc2 ,42 ,Rcpc2 ,rcpc2 +instructionset ,ARM64 ,Sve , ,43 ,Sve ,sve instructionset64bit,ARM64 ,ArmBase instructionset64bit,ARM64 ,AdvSimd @@ -177,6 +178,7 @@ instructionset64bit,ARM64 ,Dp instructionset64bit,ARM64 ,Rdm instructionset64bit,ARM64 ,Sha1 instructionset64bit,ARM64 ,Sha256 +instructionset64bit,ARM64 ,Sve vectorinstructionset,ARM64,Vector64 vectorinstructionset,ARM64,Vector128 @@ -191,6 +193,7 @@ implication ,ARM64 ,Sha256 ,ArmBase implication ,ARM64 ,Vector64 ,AdvSimd implication ,ARM64 ,Vector128 ,AdvSimd implication ,ARM64 ,VectorT128 ,AdvSimd +implication ,ARM64 ,Sve ,AdvSimd ; ,name and aliases ,archs ,lower baselines included by implication ; diff --git a/src/coreclr/vm/codeman.cpp b/src/coreclr/vm/codeman.cpp index 4dddb619675568..35c1f0cfebc044 100644 --- a/src/coreclr/vm/codeman.cpp +++ b/src/coreclr/vm/codeman.cpp @@ -1511,6 +1511,11 @@ void EEJitManager::SetCpuInfo() CPUCompileFlags.Set(InstructionSet_Sha256); } + if (((cpuFeatures & ARM64IntrinsicConstants_Sve) != 0) && CLRConfig::GetConfigValue(CLRConfig::EXTERNAL_EnableArm64Sve)) + { + CPUCompileFlags.Set(InstructionSet_Sve); + } + // DCZID_EL0<4> (DZP) indicates whether use of DC ZVA instructions is permitted (0) or prohibited (1). // DCZID_EL0<3:0> (BS) specifies Log2 of the block size in words. // diff --git a/src/libraries/System.Private.CoreLib/src/ILLink/ILLink.Substitutions.NoArmIntrinsics.xml b/src/libraries/System.Private.CoreLib/src/ILLink/ILLink.Substitutions.NoArmIntrinsics.xml index 1da6f6d57d26e3..7d05d2b47a61fe 100644 --- a/src/libraries/System.Private.CoreLib/src/ILLink/ILLink.Substitutions.NoArmIntrinsics.xml +++ b/src/libraries/System.Private.CoreLib/src/ILLink/ILLink.Substitutions.NoArmIntrinsics.xml @@ -51,5 +51,11 @@ + + + + + + diff --git a/src/libraries/System.Private.CoreLib/src/System.Private.CoreLib.Shared.projitems b/src/libraries/System.Private.CoreLib/src/System.Private.CoreLib.Shared.projitems index 5e65109ddbb378..7ae63a3f7ea3f4 100644 --- a/src/libraries/System.Private.CoreLib/src/System.Private.CoreLib.Shared.projitems +++ b/src/libraries/System.Private.CoreLib/src/System.Private.CoreLib.Shared.projitems @@ -2625,6 +2625,7 @@ + @@ -2635,6 +2636,7 @@ + diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs new file mode 100644 index 00000000000000..6219779d82d0d0 --- /dev/null +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs @@ -0,0 +1,30 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#pragma warning disable IDE0060 // unused parameters +using System.Diagnostics.CodeAnalysis; +using System.Runtime.CompilerServices; + +namespace System.Runtime.Intrinsics.Arm +{ + /// + /// This class provides access to the ARM SVE hardware instructions via intrinsics + /// + [CLSCompliant(false)] + public abstract class Sve : AdvSimd + { + internal Sve() { } + + public static new bool IsSupported { [Intrinsic] get => false; } + + [Intrinsic] + public new abstract class Arm64 : AdvSimd.Arm64 + { + internal Arm64() { } + + public static new bool IsSupported { [Intrinsic] get => false; } + } + + // Methods go here. + } +} diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs new file mode 100644 index 00000000000000..597c76e081f46f --- /dev/null +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs @@ -0,0 +1,32 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +using System.Diagnostics.CodeAnalysis; +using System.Runtime.CompilerServices; +using System.Runtime.Intrinsics; +using System.Numerics; + +namespace System.Runtime.Intrinsics.Arm +{ + /// + /// This class provides access to the ARM SVE hardware instructions via intrinsics + /// + [Intrinsic] + [CLSCompliant(false)] + public abstract class Sve : AdvSimd + { + internal Sve() { } + + public static new bool IsSupported { get => IsSupported; } + + [Intrinsic] + public new abstract class Arm64 : AdvSimd.Arm64 + { + internal Arm64() { } + + public static new bool IsSupported { get => IsSupported; } + } + + // Methods go here + } +} diff --git a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs index a4a86567f65ffb..ed12cdd1f7ba3a 100644 --- a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs +++ b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs @@ -4043,6 +4043,17 @@ internal Arm64() { } public static new bool IsSupported { get { throw null; } } } } + [System.CLSCompliantAttribute(false)] + public abstract partial class Sve : System.Runtime.Intrinsics.Arm.AdvSimd + { + internal Sve() { } + public static new bool IsSupported { get { throw null; } } + public new abstract partial class Arm64 : System.Runtime.Intrinsics.Arm.AdvSimd.Arm64 + { + internal Arm64() { } + public static new bool IsSupported { get { throw null; } } + } + } } namespace System.Runtime.Intrinsics.X86 { diff --git a/src/native/minipal/cpufeatures.c b/src/native/minipal/cpufeatures.c index db7e7acf3b80e0..ffe5be363a0bf5 100644 --- a/src/native/minipal/cpufeatures.c +++ b/src/native/minipal/cpufeatures.c @@ -356,6 +356,9 @@ int minipal_getcpufeatures(void) if (hwCap & HWCAP_ASIMDRDM) result |= ARM64IntrinsicConstants_Rdm; + if (hwCap & HWCAP_SVE) + result |= ARM64IntrinsicConstants_Sve; + #else // !HAVE_AUXV_HWCAP_H #if HAVE_SYSCTLBYNAME diff --git a/src/native/minipal/cpufeatures.h b/src/native/minipal/cpufeatures.h index d0f615d293d59f..3b8d0de8aa8656 100644 --- a/src/native/minipal/cpufeatures.h +++ b/src/native/minipal/cpufeatures.h @@ -57,6 +57,7 @@ enum ARM64IntrinsicConstants ARM64IntrinsicConstants_Rcpc = 0x0100, ARM64IntrinsicConstants_VectorT128 = 0x0200, ARM64IntrinsicConstants_Rcpc2 = 0x0400, + ARM64IntrinsicConstants_Sve = 0x0800, }; #include diff --git a/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Program.cs b/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Program.cs new file mode 100644 index 00000000000000..36c691e147ea98 --- /dev/null +++ b/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Program.cs @@ -0,0 +1,53 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +/****************************************************************************** + * This file is auto-generated from a template file by the GenerateTests.csx * + * script in tests\src\JIT\HardwareIntrinsics.Arm\Shared. In order to make * + * changes, please update the corresponding template and run according to the * + * directions listed in the file. * + ******************************************************************************/ + +using System; +using System.Reflection; +using System.Runtime.CompilerServices; +using System.Runtime.InteropServices; +using System.Runtime.Intrinsics; +using System.Runtime.Intrinsics.Arm; +using System.Numerics; +using Xunit; + +namespace JIT.HardwareIntrinsics.Arm._AdvSimd +{ + public static partial class Program + { + [Fact] + public static void SveTest() + { + var test = new SveTest__SveTest(); + + if (test.IsSupported) + { + Console.WriteLine("SVE is supported."); + test.Succeeded = true; + } + else + { + Console.WriteLine("SVE is not supported."); + test.Succeeded = true; + } + + if (!test.Succeeded) + { + throw new Exception("One or more scenarios did not complete as expected."); + } + } + } + + public sealed unsafe class SveTest__SveTest + { + public bool IsSupported => Sve.IsSupported && Sve.Arm64.IsSupported; + + public bool Succeeded { get; set; } + } +} diff --git a/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Sve.csproj b/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Sve.csproj new file mode 100644 index 00000000000000..9edcdffb8d6bb3 --- /dev/null +++ b/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Sve.csproj @@ -0,0 +1,15 @@ + + + + Exe + net8.0 + true + ARM64 + true + + + + + + + \ No newline at end of file From d104a4a2244ccebfb747d38d12f3c83983866448 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Thu, 16 Nov 2023 09:52:58 +0000 Subject: [PATCH 2/4] Add HWCAP_SVE define if it does not exist --- src/native/minipal/cpufeatures.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/native/minipal/cpufeatures.c b/src/native/minipal/cpufeatures.c index ffe5be363a0bf5..aeb7686dbec761 100644 --- a/src/native/minipal/cpufeatures.c +++ b/src/native/minipal/cpufeatures.c @@ -34,6 +34,9 @@ #ifndef HWCAP_ASIMDDP #define HWCAP_ASIMDDP (1 << 20) #endif +#ifndef HWCAP_SVE +#define HWCAP_SVE (1 << 22) +#endif #endif From acaf31eb9ea26173d0c273dafb5ab3ecb47a32ef Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Mon, 20 Nov 2023 16:56:43 +0000 Subject: [PATCH 3/4] Remove all API changes --- .../ILLink.Substitutions.NoArmIntrinsics.xml | 6 ---- .../System.Private.CoreLib.Shared.projitems | 2 -- .../Arm/Sve.PlatformNotSupported.cs | 30 ----------------- .../src/System/Runtime/Intrinsics/Arm/Sve.cs | 32 ------------------- .../ref/System.Runtime.Intrinsics.cs | 11 ------- 5 files changed, 81 deletions(-) delete mode 100644 src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs delete mode 100644 src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs diff --git a/src/libraries/System.Private.CoreLib/src/ILLink/ILLink.Substitutions.NoArmIntrinsics.xml b/src/libraries/System.Private.CoreLib/src/ILLink/ILLink.Substitutions.NoArmIntrinsics.xml index 7d05d2b47a61fe..1da6f6d57d26e3 100644 --- a/src/libraries/System.Private.CoreLib/src/ILLink/ILLink.Substitutions.NoArmIntrinsics.xml +++ b/src/libraries/System.Private.CoreLib/src/ILLink/ILLink.Substitutions.NoArmIntrinsics.xml @@ -51,11 +51,5 @@ - - - - - - diff --git a/src/libraries/System.Private.CoreLib/src/System.Private.CoreLib.Shared.projitems b/src/libraries/System.Private.CoreLib/src/System.Private.CoreLib.Shared.projitems index 7ae63a3f7ea3f4..5e65109ddbb378 100644 --- a/src/libraries/System.Private.CoreLib/src/System.Private.CoreLib.Shared.projitems +++ b/src/libraries/System.Private.CoreLib/src/System.Private.CoreLib.Shared.projitems @@ -2625,7 +2625,6 @@ - @@ -2636,7 +2635,6 @@ - diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs deleted file mode 100644 index 6219779d82d0d0..00000000000000 --- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs +++ /dev/null @@ -1,30 +0,0 @@ -// Licensed to the .NET Foundation under one or more agreements. -// The .NET Foundation licenses this file to you under the MIT license. - -#pragma warning disable IDE0060 // unused parameters -using System.Diagnostics.CodeAnalysis; -using System.Runtime.CompilerServices; - -namespace System.Runtime.Intrinsics.Arm -{ - /// - /// This class provides access to the ARM SVE hardware instructions via intrinsics - /// - [CLSCompliant(false)] - public abstract class Sve : AdvSimd - { - internal Sve() { } - - public static new bool IsSupported { [Intrinsic] get => false; } - - [Intrinsic] - public new abstract class Arm64 : AdvSimd.Arm64 - { - internal Arm64() { } - - public static new bool IsSupported { [Intrinsic] get => false; } - } - - // Methods go here. - } -} diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs deleted file mode 100644 index 597c76e081f46f..00000000000000 --- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs +++ /dev/null @@ -1,32 +0,0 @@ -// Licensed to the .NET Foundation under one or more agreements. -// The .NET Foundation licenses this file to you under the MIT license. - -using System.Diagnostics.CodeAnalysis; -using System.Runtime.CompilerServices; -using System.Runtime.Intrinsics; -using System.Numerics; - -namespace System.Runtime.Intrinsics.Arm -{ - /// - /// This class provides access to the ARM SVE hardware instructions via intrinsics - /// - [Intrinsic] - [CLSCompliant(false)] - public abstract class Sve : AdvSimd - { - internal Sve() { } - - public static new bool IsSupported { get => IsSupported; } - - [Intrinsic] - public new abstract class Arm64 : AdvSimd.Arm64 - { - internal Arm64() { } - - public static new bool IsSupported { get => IsSupported; } - } - - // Methods go here - } -} diff --git a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs index ed12cdd1f7ba3a..a4a86567f65ffb 100644 --- a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs +++ b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs @@ -4043,17 +4043,6 @@ internal Arm64() { } public static new bool IsSupported { get { throw null; } } } } - [System.CLSCompliantAttribute(false)] - public abstract partial class Sve : System.Runtime.Intrinsics.Arm.AdvSimd - { - internal Sve() { } - public static new bool IsSupported { get { throw null; } } - public new abstract partial class Arm64 : System.Runtime.Intrinsics.Arm.AdvSimd.Arm64 - { - internal Arm64() { } - public static new bool IsSupported { get { throw null; } } - } - } } namespace System.Runtime.Intrinsics.X86 { From 47a4c25dd79565f3d87b7114681dad8e7a14c826 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Wed, 22 Nov 2023 09:53:11 +0000 Subject: [PATCH 4/4] Remove InstructionSet additions --- src/coreclr/inc/clrconfigvalues.h | 1 - src/coreclr/inc/corinfoinstructionset.h | 31 +++-------- src/coreclr/inc/jiteeversionguid.h | 12 ++--- src/coreclr/inc/readytoruninstructionset.h | 1 - src/coreclr/jit/compiler.cpp | 5 -- src/coreclr/jit/hwintrinsicarm64.cpp | 8 --- src/coreclr/jit/jitconfigvalues.h | 1 - .../Compiler/HardwareIntrinsicHelpers.cs | 5 -- .../Runtime/ReadyToRunInstructionSet.cs | 1 - .../Runtime/ReadyToRunInstructionSetHelper.cs | 2 - .../JitInterface/CorInfoInstructionSet.cs | 40 +++----------- .../ThunkGenerator/InstructionSetDesc.txt | 3 -- src/coreclr/vm/codeman.cpp | 5 -- src/native/minipal/cpufeatures.c | 6 --- src/native/minipal/cpufeatures.h | 1 - .../JIT/HardwareIntrinsics/Arm/Sve/Program.cs | 53 ------------------- .../JIT/HardwareIntrinsics/Arm/Sve/Sve.csproj | 15 ------ 17 files changed, 22 insertions(+), 168 deletions(-) delete mode 100644 src/tests/JIT/HardwareIntrinsics/Arm/Sve/Program.cs delete mode 100644 src/tests/JIT/HardwareIntrinsics/Arm/Sve/Sve.csproj diff --git a/src/coreclr/inc/clrconfigvalues.h b/src/coreclr/inc/clrconfigvalues.h index 8be4aaa8eeef4f..c556d45c495894 100644 --- a/src/coreclr/inc/clrconfigvalues.h +++ b/src/coreclr/inc/clrconfigvalues.h @@ -798,7 +798,6 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sha1, W("EnableArm64Sh RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sha256, W("EnableArm64Sha256"), 1, "Allows Arm64 Sha256+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Rcpc, W("EnableArm64Rcpc"), 1, "Allows Arm64 Rcpc+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Rcpc2, W("EnableArm64Rcpc2"), 1, "Allows Arm64 Rcpc2+ hardware intrinsics to be disabled") -RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sve, W("EnableArm64Sve"), 1, "Allows Arm64 SVE hardware intrinsics to be disabled") #endif /// diff --git a/src/coreclr/inc/corinfoinstructionset.h b/src/coreclr/inc/corinfoinstructionset.h index e24bfab038ce0a..2ffd9bf6873201 100644 --- a/src/coreclr/inc/corinfoinstructionset.h +++ b/src/coreclr/inc/corinfoinstructionset.h @@ -31,16 +31,14 @@ enum CORINFO_InstructionSet InstructionSet_Rcpc=13, InstructionSet_VectorT128=14, InstructionSet_Rcpc2=15, - InstructionSet_Sve=16, - InstructionSet_ArmBase_Arm64=17, - InstructionSet_AdvSimd_Arm64=18, - InstructionSet_Aes_Arm64=19, - InstructionSet_Crc32_Arm64=20, - InstructionSet_Dp_Arm64=21, - InstructionSet_Rdm_Arm64=22, - InstructionSet_Sha1_Arm64=23, - InstructionSet_Sha256_Arm64=24, - InstructionSet_Sve_Arm64=25, + InstructionSet_ArmBase_Arm64=16, + InstructionSet_AdvSimd_Arm64=17, + InstructionSet_Aes_Arm64=18, + InstructionSet_Crc32_Arm64=19, + InstructionSet_Dp_Arm64=20, + InstructionSet_Rdm_Arm64=21, + InstructionSet_Sha1_Arm64=22, + InstructionSet_Sha256_Arm64=23, #endif // TARGET_ARM64 #ifdef TARGET_AMD64 InstructionSet_X86Base=1, @@ -284,8 +282,6 @@ struct CORINFO_InstructionSetFlags AddInstructionSet(InstructionSet_Sha1_Arm64); if (HasInstructionSet(InstructionSet_Sha256)) AddInstructionSet(InstructionSet_Sha256_Arm64); - if (HasInstructionSet(InstructionSet_Sve)) - AddInstructionSet(InstructionSet_Sve_Arm64); #endif // TARGET_ARM64 #ifdef TARGET_AMD64 if (HasInstructionSet(InstructionSet_X86Base)) @@ -398,10 +394,6 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins resultflags.RemoveInstructionSet(InstructionSet_Sha256); if (resultflags.HasInstructionSet(InstructionSet_Sha256_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Sha256)) resultflags.RemoveInstructionSet(InstructionSet_Sha256_Arm64); - if (resultflags.HasInstructionSet(InstructionSet_Sve) && !resultflags.HasInstructionSet(InstructionSet_Sve_Arm64)) - resultflags.RemoveInstructionSet(InstructionSet_Sve); - if (resultflags.HasInstructionSet(InstructionSet_Sve_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Sve)) - resultflags.RemoveInstructionSet(InstructionSet_Sve_Arm64); if (resultflags.HasInstructionSet(InstructionSet_AdvSimd) && !resultflags.HasInstructionSet(InstructionSet_ArmBase)) resultflags.RemoveInstructionSet(InstructionSet_AdvSimd); if (resultflags.HasInstructionSet(InstructionSet_Aes) && !resultflags.HasInstructionSet(InstructionSet_ArmBase)) @@ -422,8 +414,6 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins resultflags.RemoveInstructionSet(InstructionSet_Vector128); if (resultflags.HasInstructionSet(InstructionSet_VectorT128) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd)) resultflags.RemoveInstructionSet(InstructionSet_VectorT128); - if (resultflags.HasInstructionSet(InstructionSet_Sve) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd)) - resultflags.RemoveInstructionSet(InstructionSet_Sve); #endif // TARGET_ARM64 #ifdef TARGET_AMD64 if (resultflags.HasInstructionSet(InstructionSet_X86Base) && !resultflags.HasInstructionSet(InstructionSet_X86Base_X64)) @@ -774,10 +764,6 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet) return "VectorT128"; case InstructionSet_Rcpc2 : return "Rcpc2"; - case InstructionSet_Sve : - return "Sve"; - case InstructionSet_Sve_Arm64 : - return "Sve_Arm64"; #endif // TARGET_ARM64 #ifdef TARGET_AMD64 case InstructionSet_X86Base : @@ -1012,7 +998,6 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst case READYTORUN_INSTRUCTION_Rcpc: return InstructionSet_Rcpc; case READYTORUN_INSTRUCTION_VectorT128: return InstructionSet_VectorT128; case READYTORUN_INSTRUCTION_Rcpc2: return InstructionSet_Rcpc2; - case READYTORUN_INSTRUCTION_Sve: return InstructionSet_Sve; #endif // TARGET_ARM64 #ifdef TARGET_AMD64 case READYTORUN_INSTRUCTION_X86Base: return InstructionSet_X86Base; diff --git a/src/coreclr/inc/jiteeversionguid.h b/src/coreclr/inc/jiteeversionguid.h index 139ec31efae5d4..70960ff577ee8a 100644 --- a/src/coreclr/inc/jiteeversionguid.h +++ b/src/coreclr/inc/jiteeversionguid.h @@ -43,13 +43,13 @@ typedef const GUID *LPCGUID; #define GUID_DEFINED #endif // !GUID_DEFINED -constexpr GUID JITEEVersionIdentifier = { /* e15e62ce-d9c6-418a-a5a7-26ad17fcf4bf */ - 0xe15e62ce, - 0xd9c6, - 0x418a, - {0xa5, 0xa7, 0x26, 0xad, 0x17, 0xfc, 0xf4, 0xbf} +constexpr GUID JITEEVersionIdentifier = { /* a2974440-e8ee-4d95-9e6e-799a330be1a0 */ + 0xa2974440, + 0xe8ee, + 0x4d95, + {0x9e, 0x6e, 0x79, 0x9a, 0x33, 0x0b, 0xe1, 0xa0} }; - + ////////////////////////////////////////////////////////////////////////////////////////////////////////// // // END JITEEVersionIdentifier diff --git a/src/coreclr/inc/readytoruninstructionset.h b/src/coreclr/inc/readytoruninstructionset.h index 4ec3b030ae5bbb..190fe4b516617e 100644 --- a/src/coreclr/inc/readytoruninstructionset.h +++ b/src/coreclr/inc/readytoruninstructionset.h @@ -51,7 +51,6 @@ enum ReadyToRunInstructionSet READYTORUN_INSTRUCTION_VectorT256=40, READYTORUN_INSTRUCTION_VectorT512=41, READYTORUN_INSTRUCTION_Rcpc2=42, - READYTORUN_INSTRUCTION_Sve=43, }; diff --git a/src/coreclr/jit/compiler.cpp b/src/coreclr/jit/compiler.cpp index d4509bab4e6560..355403baa92684 100644 --- a/src/coreclr/jit/compiler.cpp +++ b/src/coreclr/jit/compiler.cpp @@ -6013,11 +6013,6 @@ int Compiler::compCompile(CORINFO_MODULE_HANDLE classPtr, { instructionSetFlags.AddInstructionSet(InstructionSet_Dczva); } - - if (JitConfig.EnableArm64Sve() != 0) - { - instructionSetFlags.AddInstructionSet(InstructionSet_Sve); - } #elif defined(TARGET_XARCH) if (JitConfig.EnableHWIntrinsic() != 0) { diff --git a/src/coreclr/jit/hwintrinsicarm64.cpp b/src/coreclr/jit/hwintrinsicarm64.cpp index 3394e24373bb3f..3ac9792c8eb072 100644 --- a/src/coreclr/jit/hwintrinsicarm64.cpp +++ b/src/coreclr/jit/hwintrinsicarm64.cpp @@ -34,8 +34,6 @@ static CORINFO_InstructionSet Arm64VersionOfIsa(CORINFO_InstructionSet isa) return InstructionSet_Sha256_Arm64; case InstructionSet_Rdm: return InstructionSet_Rdm_Arm64; - case InstructionSet_Sve: - return InstructionSet_Sve_Arm64; default: return InstructionSet_NONE; } @@ -99,10 +97,6 @@ static CORINFO_InstructionSet lookupInstructionSet(const char* className) { return InstructionSet_Sha256; } - if (strcmp(className, "Sve") == 0) - { - return InstructionSet_Sve; - } } else if (className[0] == 'V') { @@ -172,8 +166,6 @@ bool HWIntrinsicInfo::isFullyImplementedIsa(CORINFO_InstructionSet isa) case InstructionSet_Sha1_Arm64: case InstructionSet_Sha256: case InstructionSet_Sha256_Arm64: - case InstructionSet_Sve: - case InstructionSet_Sve_Arm64: case InstructionSet_Vector64: case InstructionSet_Vector128: return true; diff --git a/src/coreclr/jit/jitconfigvalues.h b/src/coreclr/jit/jitconfigvalues.h index 38279e6853c1af..65afd348819e11 100644 --- a/src/coreclr/jit/jitconfigvalues.h +++ b/src/coreclr/jit/jitconfigvalues.h @@ -351,7 +351,6 @@ CONFIG_INTEGER(EnableArm64Dp, W("EnableArm64Dp"), 1) / CONFIG_INTEGER(EnableArm64Rdm, W("EnableArm64Rdm"), 1) // Allows Arm64 Rdm+ hardware intrinsics to be disabled CONFIG_INTEGER(EnableArm64Sha1, W("EnableArm64Sha1"), 1) // Allows Arm64 Sha1+ hardware intrinsics to be disabled CONFIG_INTEGER(EnableArm64Sha256, W("EnableArm64Sha256"), 1) // Allows Arm64 Sha256+ hardware intrinsics to be disabled -CONFIG_INTEGER(EnableArm64Sve, W("EnableArm64Sve"), 1) // Allows Arm64 Sve+ hardware intrinsics to be disabled #endif // clang-format on diff --git a/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs b/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs index c30736fcb6019d..1e778e97c67f3e 100644 --- a/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs +++ b/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs @@ -221,7 +221,6 @@ private static class Arm64IntrinsicConstants public const int Rcpc = 0x0100; public const int VectorT128 = 0x0200; public const int Rcpc2 = 0x0400; - public const int Sve = 0x0800; public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags) { @@ -245,8 +244,6 @@ public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags) builder.AddSupportedInstructionSet("rcpc"); if ((flags & Rcpc2) != 0) builder.AddSupportedInstructionSet("rcpc2"); - if ((flags & Sve) != 0) - builder.AddSupportedInstructionSet("sve"); } public static int FromInstructionSet(InstructionSet instructionSet) @@ -276,8 +273,6 @@ public static int FromInstructionSet(InstructionSet instructionSet) InstructionSet.ARM64_Atomics => Atomics, InstructionSet.ARM64_Rcpc => Rcpc, InstructionSet.ARM64_Rcpc2 => Rcpc2, - InstructionSet.ARM64_Sve => Sve, - InstructionSet.ARM64_Sve_Arm64 => Sve, // Vector Sizes InstructionSet.ARM64_VectorT128 => VectorT128, diff --git a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs index 284131d1641acc..51c1a4854d71f4 100644 --- a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs +++ b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs @@ -54,7 +54,6 @@ public enum ReadyToRunInstructionSet VectorT256=40, VectorT512=41, Rcpc2=42, - Sve=43, } } diff --git a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs index 7000b482ec604a..57629f66b9c6f5 100644 --- a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs +++ b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs @@ -46,8 +46,6 @@ public static class ReadyToRunInstructionSetHelper case InstructionSet.ARM64_Rcpc: return ReadyToRunInstructionSet.Rcpc; case InstructionSet.ARM64_VectorT128: return ReadyToRunInstructionSet.VectorT128; case InstructionSet.ARM64_Rcpc2: return ReadyToRunInstructionSet.Rcpc2; - case InstructionSet.ARM64_Sve: return ReadyToRunInstructionSet.Sve; - case InstructionSet.ARM64_Sve_Arm64: return ReadyToRunInstructionSet.Sve; default: throw new Exception("Unknown instruction set"); } diff --git a/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs b/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs index a5398c85ca0758..d7bc2e56ebd2a4 100644 --- a/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs +++ b/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs @@ -31,7 +31,6 @@ public enum InstructionSet ARM64_Rcpc = InstructionSet_ARM64.Rcpc, ARM64_VectorT128 = InstructionSet_ARM64.VectorT128, ARM64_Rcpc2 = InstructionSet_ARM64.Rcpc2, - ARM64_Sve = InstructionSet_ARM64.Sve, ARM64_ArmBase_Arm64 = InstructionSet_ARM64.ArmBase_Arm64, ARM64_AdvSimd_Arm64 = InstructionSet_ARM64.AdvSimd_Arm64, ARM64_Aes_Arm64 = InstructionSet_ARM64.Aes_Arm64, @@ -40,7 +39,6 @@ public enum InstructionSet ARM64_Rdm_Arm64 = InstructionSet_ARM64.Rdm_Arm64, ARM64_Sha1_Arm64 = InstructionSet_ARM64.Sha1_Arm64, ARM64_Sha256_Arm64 = InstructionSet_ARM64.Sha256_Arm64, - ARM64_Sve_Arm64 = InstructionSet_ARM64.Sve_Arm64, X64_X86Base = InstructionSet_X64.X86Base, X64_SSE = InstructionSet_X64.SSE, X64_SSE2 = InstructionSet_X64.SSE2, @@ -189,16 +187,14 @@ public enum InstructionSet_ARM64 Rcpc = 13, VectorT128 = 14, Rcpc2 = 15, - Sve = 16, - ArmBase_Arm64 = 17, - AdvSimd_Arm64 = 18, - Aes_Arm64 = 19, - Crc32_Arm64 = 20, - Dp_Arm64 = 21, - Rdm_Arm64 = 22, - Sha1_Arm64 = 23, - Sha256_Arm64 = 24, - Sve_Arm64 = 25, + ArmBase_Arm64 = 16, + AdvSimd_Arm64 = 17, + Aes_Arm64 = 18, + Crc32_Arm64 = 19, + Dp_Arm64 = 20, + Rdm_Arm64 = 21, + Sha1_Arm64 = 22, + Sha256_Arm64 = 23, } public enum InstructionSet_X64 @@ -529,10 +525,6 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target resultflags.AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64); if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sha256_Arm64)) resultflags.AddInstructionSet(InstructionSet.ARM64_Sha256); - if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve)) - resultflags.AddInstructionSet(InstructionSet.ARM64_Sve_Arm64); - if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve_Arm64)) - resultflags.AddInstructionSet(InstructionSet.ARM64_Sve); if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd)) resultflags.AddInstructionSet(InstructionSet.ARM64_ArmBase); if (resultflags.HasInstructionSet(InstructionSet.ARM64_Aes)) @@ -553,8 +545,6 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd); if (resultflags.HasInstructionSet(InstructionSet.ARM64_VectorT128)) resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd); - if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve)) - resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd); break; case TargetArchitecture.X64: @@ -884,8 +874,6 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe resultflags.AddInstructionSet(InstructionSet.ARM64_Sha1); if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sha256_Arm64)) resultflags.AddInstructionSet(InstructionSet.ARM64_Sha256); - if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve_Arm64)) - resultflags.AddInstructionSet(InstructionSet.ARM64_Sve); if (resultflags.HasInstructionSet(InstructionSet.ARM64_ArmBase)) resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd); if (resultflags.HasInstructionSet(InstructionSet.ARM64_ArmBase)) @@ -906,8 +894,6 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe resultflags.AddInstructionSet(InstructionSet.ARM64_Vector128); if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd)) resultflags.AddInstructionSet(InstructionSet.ARM64_VectorT128); - if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd)) - resultflags.AddInstructionSet(InstructionSet.ARM64_Sve); break; case TargetArchitecture.X64: @@ -1212,7 +1198,6 @@ public static IEnumerable ArchitectureToValidInstructionSets yield return new InstructionSetInfo("rcpc", "", InstructionSet.ARM64_Rcpc, true); yield return new InstructionSetInfo("vectort128", "VectorT128", InstructionSet.ARM64_VectorT128, true); yield return new InstructionSetInfo("rcpc2", "", InstructionSet.ARM64_Rcpc2, true); - yield return new InstructionSetInfo("sve", "Sve", InstructionSet.ARM64_Sve, true); break; case TargetArchitecture.X64: @@ -1315,8 +1300,6 @@ public void Set64BitInstructionSetVariants(TargetArchitecture architecture) AddInstructionSet(InstructionSet.ARM64_Sha1_Arm64); if (HasInstructionSet(InstructionSet.ARM64_Sha256)) AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64); - if (HasInstructionSet(InstructionSet.ARM64_Sve)) - AddInstructionSet(InstructionSet.ARM64_Sve_Arm64); break; case TargetArchitecture.X64: @@ -1399,7 +1382,6 @@ public void Set64BitInstructionSetVariantsUnconditionally(TargetArchitecture arc AddInstructionSet(InstructionSet.ARM64_Rdm_Arm64); AddInstructionSet(InstructionSet.ARM64_Sha1_Arm64); AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64); - AddInstructionSet(InstructionSet.ARM64_Sve_Arm64); break; case TargetArchitecture.X64: @@ -1569,12 +1551,6 @@ public static InstructionSet LookupPlatformIntrinsicInstructionSet(TargetArchite case "VectorT128": { return InstructionSet.ARM64_VectorT128; } - case "Sve": - if (nestedTypeName == "Arm64") - { return InstructionSet.ARM64_Sve_Arm64; } - else - { return InstructionSet.ARM64_Sve; } - } break; diff --git a/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt b/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt index 7b6e15b87bd84a..ba4db589c81a0f 100644 --- a/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt +++ b/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt @@ -168,7 +168,6 @@ instructionset ,ARM64 , , , ,Dczva instructionset ,ARM64 , ,Rcpc ,26 ,Rcpc ,rcpc instructionset ,ARM64 ,VectorT128 , ,39 ,VectorT128 ,vectort128 instructionset ,ARM64 , ,Rcpc2 ,42 ,Rcpc2 ,rcpc2 -instructionset ,ARM64 ,Sve , ,43 ,Sve ,sve instructionset64bit,ARM64 ,ArmBase instructionset64bit,ARM64 ,AdvSimd @@ -178,7 +177,6 @@ instructionset64bit,ARM64 ,Dp instructionset64bit,ARM64 ,Rdm instructionset64bit,ARM64 ,Sha1 instructionset64bit,ARM64 ,Sha256 -instructionset64bit,ARM64 ,Sve vectorinstructionset,ARM64,Vector64 vectorinstructionset,ARM64,Vector128 @@ -193,7 +191,6 @@ implication ,ARM64 ,Sha256 ,ArmBase implication ,ARM64 ,Vector64 ,AdvSimd implication ,ARM64 ,Vector128 ,AdvSimd implication ,ARM64 ,VectorT128 ,AdvSimd -implication ,ARM64 ,Sve ,AdvSimd ; ,name and aliases ,archs ,lower baselines included by implication ; diff --git a/src/coreclr/vm/codeman.cpp b/src/coreclr/vm/codeman.cpp index 35c1f0cfebc044..4dddb619675568 100644 --- a/src/coreclr/vm/codeman.cpp +++ b/src/coreclr/vm/codeman.cpp @@ -1511,11 +1511,6 @@ void EEJitManager::SetCpuInfo() CPUCompileFlags.Set(InstructionSet_Sha256); } - if (((cpuFeatures & ARM64IntrinsicConstants_Sve) != 0) && CLRConfig::GetConfigValue(CLRConfig::EXTERNAL_EnableArm64Sve)) - { - CPUCompileFlags.Set(InstructionSet_Sve); - } - // DCZID_EL0<4> (DZP) indicates whether use of DC ZVA instructions is permitted (0) or prohibited (1). // DCZID_EL0<3:0> (BS) specifies Log2 of the block size in words. // diff --git a/src/native/minipal/cpufeatures.c b/src/native/minipal/cpufeatures.c index aeb7686dbec761..db7e7acf3b80e0 100644 --- a/src/native/minipal/cpufeatures.c +++ b/src/native/minipal/cpufeatures.c @@ -34,9 +34,6 @@ #ifndef HWCAP_ASIMDDP #define HWCAP_ASIMDDP (1 << 20) #endif -#ifndef HWCAP_SVE -#define HWCAP_SVE (1 << 22) -#endif #endif @@ -359,9 +356,6 @@ int minipal_getcpufeatures(void) if (hwCap & HWCAP_ASIMDRDM) result |= ARM64IntrinsicConstants_Rdm; - if (hwCap & HWCAP_SVE) - result |= ARM64IntrinsicConstants_Sve; - #else // !HAVE_AUXV_HWCAP_H #if HAVE_SYSCTLBYNAME diff --git a/src/native/minipal/cpufeatures.h b/src/native/minipal/cpufeatures.h index 3b8d0de8aa8656..d0f615d293d59f 100644 --- a/src/native/minipal/cpufeatures.h +++ b/src/native/minipal/cpufeatures.h @@ -57,7 +57,6 @@ enum ARM64IntrinsicConstants ARM64IntrinsicConstants_Rcpc = 0x0100, ARM64IntrinsicConstants_VectorT128 = 0x0200, ARM64IntrinsicConstants_Rcpc2 = 0x0400, - ARM64IntrinsicConstants_Sve = 0x0800, }; #include diff --git a/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Program.cs b/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Program.cs deleted file mode 100644 index 36c691e147ea98..00000000000000 --- a/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Program.cs +++ /dev/null @@ -1,53 +0,0 @@ -// Licensed to the .NET Foundation under one or more agreements. -// The .NET Foundation licenses this file to you under the MIT license. - -/****************************************************************************** - * This file is auto-generated from a template file by the GenerateTests.csx * - * script in tests\src\JIT\HardwareIntrinsics.Arm\Shared. In order to make * - * changes, please update the corresponding template and run according to the * - * directions listed in the file. * - ******************************************************************************/ - -using System; -using System.Reflection; -using System.Runtime.CompilerServices; -using System.Runtime.InteropServices; -using System.Runtime.Intrinsics; -using System.Runtime.Intrinsics.Arm; -using System.Numerics; -using Xunit; - -namespace JIT.HardwareIntrinsics.Arm._AdvSimd -{ - public static partial class Program - { - [Fact] - public static void SveTest() - { - var test = new SveTest__SveTest(); - - if (test.IsSupported) - { - Console.WriteLine("SVE is supported."); - test.Succeeded = true; - } - else - { - Console.WriteLine("SVE is not supported."); - test.Succeeded = true; - } - - if (!test.Succeeded) - { - throw new Exception("One or more scenarios did not complete as expected."); - } - } - } - - public sealed unsafe class SveTest__SveTest - { - public bool IsSupported => Sve.IsSupported && Sve.Arm64.IsSupported; - - public bool Succeeded { get; set; } - } -} diff --git a/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Sve.csproj b/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Sve.csproj deleted file mode 100644 index 9edcdffb8d6bb3..00000000000000 --- a/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Sve.csproj +++ /dev/null @@ -1,15 +0,0 @@ - - - - Exe - net8.0 - true - ARM64 - true - - - - - - - \ No newline at end of file