From 09285449678cbde75f4fc8bc8412bf96cab4ca9c Mon Sep 17 00:00:00 2001
From: fangrh <48038692+fangrh@users.noreply.github.com>
Date: Tue, 25 Apr 2023 09:31:54 +0800
Subject: [PATCH 1/2] Correct "Bool" error in SpinalHDL v1.6.0+?

The written form of "Bool" is not supported in SpinalHDL versions equal to or greater than 1.6.0, so the template has been modified.
---
 src/main/scala/mylib/MyTopLevel.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/mylib/MyTopLevel.scala b/src/main/scala/mylib/MyTopLevel.scala
index 196d09a..5d42337 100644
--- a/src/main/scala/mylib/MyTopLevel.scala
+++ b/src/main/scala/mylib/MyTopLevel.scala
@@ -26,9 +26,9 @@ import scala.util.Random
 //Hardware definition
 class MyTopLevel extends Component {
   val io = new Bundle {
-    val cond0 = in  Bool
-    val cond1 = in  Bool
-    val flag  = out Bool
+    val cond0 = in  Bool()
+    val cond1 = in  Bool()
+    val flag  = out Bool()
     val state = out UInt(8 bits)
   }
   val counter = Reg(UInt(8 bits)) init(0)
@@ -64,4 +64,4 @@ object MyTopLevelVerilogWithCustomConfig {
   def main(args: Array[String]) {
     MySpinalConfig.generateVerilog(new MyTopLevel)
   }
-}
\ No newline at end of file
+}

From 7c6cbc9f9e1719fe5f2c73e8854994f7e86f9198 Mon Sep 17 00:00:00 2001
From: fangrh <48038692+fangrh@users.noreply.github.com>
Date: Tue, 25 Apr 2023 09:34:56 +0800
Subject: [PATCH 2/2] Revert "Correct "Bool" error in SpinalHDL v1.6.0+?"

---
 src/main/scala/mylib/MyTopLevel.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/mylib/MyTopLevel.scala b/src/main/scala/mylib/MyTopLevel.scala
index 5d42337..196d09a 100644
--- a/src/main/scala/mylib/MyTopLevel.scala
+++ b/src/main/scala/mylib/MyTopLevel.scala
@@ -26,9 +26,9 @@ import scala.util.Random
 //Hardware definition
 class MyTopLevel extends Component {
   val io = new Bundle {
-    val cond0 = in  Bool()
-    val cond1 = in  Bool()
-    val flag  = out Bool()
+    val cond0 = in  Bool
+    val cond1 = in  Bool
+    val flag  = out Bool
     val state = out UInt(8 bits)
   }
   val counter = Reg(UInt(8 bits)) init(0)
@@ -64,4 +64,4 @@ object MyTopLevelVerilogWithCustomConfig {
   def main(args: Array[String]) {
     MySpinalConfig.generateVerilog(new MyTopLevel)
   }
-}
+}
\ No newline at end of file